Phase lock loop

[Altera_Forum]

I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???

[Altera_Forum]

You didn't mention the intended output of the PLL (frequency, waveform). In power electronic applications, a 50/60 Hz PLL with quadrature sine output is a common building block. It can be implemented with a NCO, phase detector (multiplier with averager/integrator) and a PI controller. In contrast to the high frequency analog PLL provided for FPGA clocking, the complete PLL function is performed by digital signal processing. Thus it's called digital or all digital PLL (DPLL/ADPLL).

[Altera_Forum]

My output should be same as input(60 HZ). But fpga has in built pll, whose internal clock works at Mhz. So Hz and Mhz cant be synchronized.  

I was trying to implement in zero buffer mode using a[/U][/U]ltpll megafunction But its input range is in MHz. It is possible for me to implement in fpga reconfig methods.

[Altera_Forum]

--- Quote Start ---  But fpga has in built pll, whose internal clock works at Mhz. So Hz and Mhz cant be synchronized.  --- Quote End ---   How do you want to achieve synchronization? Did you notice the PLL input frequency range? Minimum input frequency, set by the PFD properties, is 10 MHz. That's why I suggested an ADPLL design.

[Altera_Forum]

Thank u so much for the reply. it is possible for me to implement ADPLL in fpga, using megafunction wizard? If not , can we code in vhdl.  

Your help is appreciated..

[Altera_Forum]

There's no Altera MegaFunction providing ADPLL functionality. There has been a previous forum discussion related to an ADPLL code sourced from Best's PLL text book, if I understand right. The original poster said it doesn't work. Apart from this particular code, it's of course possible to implement the ADPLL concept from literature in VHDL. I have implemented a PLL as sketched in my above post. But it's part of a larger customer design and neither dedicated to the public domain nor written to be instructive. 

 http://www.alteraforum.com/forum/showthread.php?t=3310

[Altera_Forum]

what is diff between dpll and adpll? 

How we can implement adpll in fpga? Using reconfig methods can we implement adpll at 60 HZ input freq and output freq is also same.

[Altera_Forum]

In Best's PLL book, ADPLL is designating PLLs with a software VCO (NCO), while DPLL means PLLs with analog VCO and digital phase detector. In this view, the PLLs implemented in Altera FPGAs are DPLLs, too. But in other literature, the term DPLL is also used for software PLLs 

 The built-in FPGA PLLs are only suited for input frequencies in the MHz range by the design of their phase detector and dimensioning of the PLL loop filter. There's effectively no chance to synchronize them to 60 Hz input.  I previously mentioned the basic components of an ADPLL design. Details can be found in literature, e.g. Roland E. Best, phase-locked loops, design, simulation and applications. Unfortunately, I don't have a ready-to-use HDL code example.

[Altera_Forum]

1.Does Altera fpga DE2 board has in built analog to digital converter? 

2.I want to synchronize 60 hz input , from the following which will be the suitable phase frequency detector for my requirement?  a. Flip-flop Counter PD  b.Nyquist Rate Phase Detector  c.Zero-Crossing Phase Detector  d.Hilbert Transform Phase Detector  e.Digital-Averaging Phase Detector   Your help is really appreciated

[Altera_Forum]

Phase detector selection mainly depends on the type of input signal, that you didn't mention yet. For an analog input signal (sine waveform), I prefer either a simple multiplier ("Nyquist rate detector") or a quadrature multiplier with amlitude scaling ("Averaging phase detector"). For a digital input clock, a FF counter or XOR phase detector could be used. 

 I just noticed, that Altera (previously?) had an adpll reference design shipped with the NCO IP. The description briefly mentions the involved building blocks: http://www.altera.com/products/ip/altera/t-alt-adpll.html

[Altera_Forum]

My input is sine wave which is 60 hz. my output should be exactly synchronized with output having 60 Hz digital output.  

 The input should first be given to analog to didgital converter right.   Does altera fpga support inbuilt analog to digital converter??

[Altera_Forum]

--- Quote Start ---  Does altera fpga support inbuilt analog to digital converter??  --- Quote End ---   At the system level, an ADC is sending parallel data at a predefined rate, there's no particular support needed for it. Some Altera Dev Kits have high speed ADC, they just send the data in parallel. Slow ADC usually have serial interfaces, e.g. SPI. You have to convert the serial data to parallel. In my view, a SPI interface isn't more than a few lines of VHDL code, I don't expect particluar support for it.  You could however use the audio codec supplied with several Dev Kits, e.g. Terasic DE2 to convert the input signal. The demonstration code for the respective boards basically shows how to use the converter (but not in a really instructive way).  The sense of processing an analog 60 Hz input signal strongly depends on the overall system function. If you only need the fundamental frequency and phase information, a bandpass filter with a succeeding comparator feeding a digital phase detector can do the same. If the analog input is however used for other purposes (measurement, control of grid tied inverter) it's most simple to feed the analog waveform to the PLL.

[Altera_Forum]

Thank u so much for your reply. I am bit confused by your answer, since i am new to altera.  

 I have an analog input signal of 60 Hz. I should lock the input signal with same phase and frequency and get the output in digital form. I should multiply the output(digital pulse with 60 HZ) to get in MHz. Then i should perform pulse width modulation based on the sine wave table and the final pulse i should feed in inverter. This is my overall task.   Should i give the analog input signal of 60 Hz in 40 pin input/output port . Then by using vhdl code i should convert 60 HZ analog to digital.

[Altera_Forum]

I'm not sure, if you necessarily need a PLL for synchronizing a PWM generator to a 60 Hz input. If the 60 Hz input is from the mains power line, the frequency variations will be very low. So generating the PWM timing from a crystal and only synchronizing it to the 60 Hz reference should be sufficient.

[Altera_Forum]

The frequency variations will be very low. To get exact pwm with reference to the input , pll is needed.  

 I just want to know how to convert my analog input to digital . it can be implemented only vhdl code or any other inbuilt adc is available in altera fpga.  Your help is really appreciated

[Altera_Forum]

No Altera FPGA has built-in ADC. As I mentioned, some development kits have an ADC, but because of the large range of differenr requirements and different available devices, designer use to select them according to the application. 

   --- Quote Start ---  To get exact pwm with reference to the input , pll is needed.  --- Quote End ---   I don't generally agree. But many inverter control concepts are possible.

[Altera_Forum]

Since my input is in 60 Hz will below PDF block diagram works for me to get synchronization of the input. 

 http://users.ece.gatech.edu/~jskenney/l080-adpll(2up).pdf (http://users.ece.gatech.edu/%7ejskenney/l080-adpll%282up%29.pdf)  file:///C:/DOCUME%7E1/kvvani/LOCALS%7E1/Temp/moz-screenshot.jpg In attached pdf on (page file:///C:/DOCUME%7E1/kvvani/LOCALS%7E1/Temp/moz-screenshot-1.jpg 080-18) example 1 .  Kindly help me

[Altera_Forum]

--- Quote Start ---  Since my input is in 60 Hz will below PDF block diagram works for me to get synchronization of the input.  http://users.ece.gatech.edu/~jskenney/l080-adpll(2up).pdf (http://users.ece.gatech.edu/%7ejskenney/l080-adpll%282up%29.pdf)  In attached pdf on (page 080-18) example 1 .  Kindly help me

[Altera_Forum]

Sounds like a fun project. Generally, the PLL phase detector types are chosen for their characteristics in an analog PLLs. For a digital PLL you can implement whatever works in your design. If you have an ADC input, you will have to use an average of the input for the zero crossing. If you are using a comparitor, the input will be a simple zero or one. These outputs can be further filtered to reduce noise. From these inputs you can implement the logic of any of the phase detector types. 

 Texas instruments has some documentation on their sn74ls297, which is a diigital PLL part. This is really a control problem and should be properly characterized as such. Especially you if you need zero phase difference between the input/output.

[Altera_Forum]

--- Quote Start ---  will below PDF block diagram works for me to get synchronization of the input  --- Quote End ---   Basically yes. You have to care, that the digital input, e.g. sourced from a comparator, doesn't produce multiple edges. A phase detector, that evaluates the fundamental of the input signal (e.g. "Nyquist rate") or averages the sign (XOR phase-detector, e.g. page 080-27) would be more robust against distorted input signals.

[Altera_Forum]

--- Quote Start ---  Basically yes. You have to care, that the digital input, e.g. sourced from a comparator, doesn't produce multiple edges. A phase detector, that evaluates the fundamental of the input signal (e.g. "Nyquist rate") or averages the sign (XOR phase-detector, e.g. page 080-27) would be more robust against distorted input signals.  --- Quote End ---     So instead of Jk flip flop , i can go ahead with XOR PHASE-DETECTOR right? My input is 60 Hz (variable) analog signal. In the block diagram i have few questions, since my input is 60 HZ  1. how i should choose my fC(INPUT to variable N counter)  2. Can explain the digital controlled oscillator part?   Ur help is really appreciated.