Qsys problem in connecting Avalon-MM master and slave with different symbol widths

[Altera_Forum]

hi, i cannot connect avalon-mm master with a symbol width of 8 and avalon-mm slave with a symbol width of 9. 

 i am trying to connect a 128-bit width master with 8-bit symbol of a clock crossing bridge to a 72-bit width slave with 9-bit symbol of qdrii+ sram controller. when connecting them, qsys gives an error message "error: system.: signal m0[8] and signal avl_r[9] must have the same symbol width." i cannot change the 9-bit symbol width of the qdrii+ controller. i also have to 8-bit symbol for the bridge because it's slave is also connected to avalon-mm master of pci-express interface. could you help me?  it is okay for me to connect only 64 bits from the 72 bits of the qdrii+ controller to make a symbol width 8 bits from 9 bits.    micky

[Altera_Forum]

--- Quote Start ---  hi, i cannot connect avalon-mm master with a symbol width of 8 and avalon-mm slave with a symbol width of 9.  i am trying to connect a 128-bit width master with 8-bit symbol of a clock crossing bridge to a 72-bit width slave with 9-bit symbol of qdrii+ sram controller. when connecting them, qsys gives an error message "error: system.: signal m0[8] and signal avl_r[9] must have the same symbol width." i cannot change the 9-bit symbol width of the qdrii+ controller. i also have to 8-bit symbol for the bridge because it's slave is also connected to avalon-mm master of pci-express interface. could you help me?  it is okay for me to connect only 64 bits from the 72 bits of the qdrii+ controller to make a symbol width 8 bits from 9 bits.  micky  --- Quote End ---     I remember I had to deal with something similar when trying to configure the controller for LPDDR2. I don't have much knowledge of the QDRII controller but I assume it is the same principle. The data width of the controller interface connected to qsys bus which is in your case 72 bit wide depends upon the data width of the external interface between the memory controller and QDRII PHY. Sometimes not all the Memory pins are connected to the FPGA device so you have to be careful how many pins you actually can use.   I think at your level the best thing to do is to make a calculation of how much bandwidth you will need in order to identify how many external memory pins you can sacrifice. You might don't need to though in case you already have something like 16 bits wide interface.   Try to change the width of the external bus (i think it can be done in the memory controller interface) so the internal width will be aligned with qsys interconnect. Change your memory control pins accordingly if there aren't done automatically.

[Altera_Forum]

Hi, thanks. 

 I also think that your LPDDR2 case is similar to my QDDRII case. In the current design, it is okay to use 16 pins from 18 pins of QDRII memory. I tried to do this, but the width of the external pins to memory cannot be changed (with the symbol width). The value of "18" is fixed, and cannot be changed...  What I am trying is to export AvalonMM bus with symbol width of 8, and connect the exported ports of Qsys module to QDRII controller generated by MegaFunction Wizard.  If you have any other advices, please help me.  Micky

[Altera_Forum]

Hi, 

 I missed "generate power-of-2 data bus widths" option in the QDRII+ controller wizard. When I turned it on, I got a module with data width = 64 and symbol width = 8. Anyway, thank you for your advise!  Micky

[Altera_Forum]

I should mention that in Qsys, different cores have different data widths. The interconnexion between different widths is achieved by an Altera predefined element called Merlin Width Adapter. This element will simply not be synthesizable because it can only perform alignment between data widths within (16, 32, 64, 128, 256) at least as it seems to :) 

 You can check the source code for Merlin Width Adapter which appears to be written in system verilog and you will understand why you need a power of 2 data width.

[Altera_Forum]

Hi PoseidonElectronics, 

 Thanks to your suggestion. I will read the code generated by Qsys. I made sure that QDRII+ works correctly in our design :-)  Micky

[Altera_Forum]

Hi, 

 After all, I knew that I still had a problem of the QDRII+ controller. I connected the 64-bit read/write Avalon-MM ports of the QDRII+ controller to BAR2 of PCIe core. The PCIe core works correctly.  However, the QDRII+ core operates incorrectly. At every address, the least significand 4 bits in the 64 bits are always "0000", while the remaining 60 bits match the written 60 bits.  All the four QDRII+ SRAM @ 500MHz on Terasic DE5-NET board have the same problem. We configured different DE5-NET boards with the same bit stream, they also had the same problem.  I carefully made settings on the QDRII+ core based on the sample design by Terasic... Can anyone help me?  Many thanks,  Micky