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Anyone encountered issues with QSYS not able to generate netlist? I created a small test case with Just clocks and DDR3 (hardmacro).
It was hang while generating DDR part.
When I tried on the same version on Windows 7 it is working fine.
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Hi,
- Which Edition of quartus std/pro/lite?
- Elaborate more on device, IP used, steps & IP setting of ddr and file generated for synthesis(VHDL/Verilog)?
- Also attache some the image.
Best Regards,
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
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- Quartus Prime Version 17.1.0 Build 590 10/25/2017 Lite Edition
- I basically added the IPs in platform designer GUI. It works well on my Win7 PC using exact same quartus.
add_instance cam_avalon_s altera_avalon_mm_bridge 17.1
add_instance clkin_50MHz clock_source 17.1
add_instance ddr altera_mem_if_ddr3_emif 17.1
add_instance master_0 altera_jtag_avalon_master 17.1
add_instance pio_control altera_avalon_pio 17.1
add_instance pio_status altera_avalon_pio 17.1
add_instance spislave_0 spislave 17.1
add_instance sysclk clock_source 17.1
add_instance usb_avalon_s altera_avalon_mm_bridge 17.1
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Hi,
Sorry for the late response.
We have used Quarts 17.1 lite in windows 10 environment.
- Used Clock Source and DDR3 IP’s only.
It was successful generated.
Can you try to recreating the project or by deleting the db folder.
Best Regards,
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
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Hi,
Can you update the windows or reinstall the Quartus and check.
Best Regards,
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
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Hi,
The above scenario will be fixed by disabling one of the Windows feature as highlighted below “Windows Subsystem for Linux”.
Best Regards,
Anand Raj Shankar
(This message was posted on behalf of Intel Corporation)
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