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AVanB3
Beginner
249 Views

Quartus II apparently doesn't automatically use the simulation testfile that was made for a 4 to 1 Mux and its already in the VHDL file put in In- and output declarations to simulate input data without manually presetting the in-and outputs first?

A complete VHDL file with added testbench file of a 4to1 Mux apparently doesn't run any simulation in Quartus II 13.x ? I do not know if I still have to config all in and outputs first manually. Or that running the Testbench file on its own is possible to start the 4to1 mux simulation? (My Quartus II version is offline and there is no Help database whatsover to support any questions but it is desperately needed!)

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7 Replies
AVanB3
Beginner
206 Views

And in addition to above question.... can I download and add the Quartus II Help database somewhere for my old Quartus 13.x version. So it will Help me on my offline computer?

AVanB3
Beginner
206 Views

Hereby added the mux4to1 file with testbench part that doesn't automatically start or instruct the simulation.

sstrell
Honored Contributor II
206 Views

What tool are you using for simulation? If it's ModelSim, the testbench should be a separate file, not included with the design itself.

 

If you're using the old built-in simulation tool of Quartus, you need a .vwf file for the testbench.

 

#iwork4intel

AVanB3
Beginner
206 Views

Thanks sstrell for clearing it up a bit. I use old Quartus II 13.x version with I think the built-in Modelsim tool. And I know that Modelsim is actively installed and so working. I now have to figure out how to make this specific .vwf file and how it is locked to the design mux4to1 file. Cause the Help database in my Quartus version is no help at all because it is empty and looks for an online connection on my offline computer. (Why my other question was if it is possible to download the Help database so it is working off-line too?).

AVanB3
Beginner
192 Views

Simulating in Quartus II is still so much more difficult than it is in Xilinx ISE 14.6.

Why I have following question HOW to start a graphical testwave file in next example:

---------------------------------------
ENTITY Fig_210 IS
PORT( a,b,c: in STD_LOGIC; z: out STD_LOGIC);
END ENTITY Fig_210;
---------------------------------------
ARCHITECTURE Fig_210 of Fig_210 IS
 
SIGNAL x : STD_LOGIC;
SIGNAL y: STD_LOGIC;
 
BEGIN
 
x <= a NAND b;
y <= x OR c;
z <= a XOR y;
END ARCHITECTURE Fig_210;
 
----------------------
 
This is the answer to the first exercise from PEDRONI's book on Design and simulation in VHDL 2ed.
It compiled perfectly in Quartus II 13.1_32bit, but the book, as also other books, hardly explain HOW to make a graphical test WAVE in Quartus using Modelsim ALTERA STARTER EDITION 10.1d. And the Modelsim 10.1d opening window is completely Chinese to me.
 
Simulating is SO MUCH EASIER in Xilinx ISE 14.6 but almost impossible to do in Quartus II ! 
 
Can anyone please help me what to do exactly, because I have no ON-LINE Help and Quartus already asked me to buy/upgrade my free version Online because it runs out in its trial base timed edition somehow. And there is no Help database in the 13.1 version whatsoever! And all books and documents I found only review the easier older versions of Modelsim and Quartus II that do not compare to the later editions at all ! It is made so complex that it became impossible to use for any starter.

Thanks,
AvB.
AVanB3
Beginner
183 Views

Thanks to 9th Edition book: Digital Electronics_A practical Approach with VHDL by William Kleitz page 143, I tonight succeeded in making a working vwf graphical Wave vector Testbench file. Although the ModelSim window in itself still is far from easy and way too complex to understand with all options provided!

I noticed in the result however that in given example the Waves of x and y, being the internal SIGNAL lines, do not matter in the simulation. Output z changes only according to the manually edited Wave inputs a, b and c. Which probably is because the given ENTITY doesn't mention these. Internal x and y outputs are only mentioned in the ARCHITECTURE part of example Fig_2.10 of the above mentioned book of Pedroni 2ed. I guess that this is normal and correct?

I hope that my Quartus 13.1 version with Modelsim 10.1d keeps working without limits after my license has expired after the program is not online upgraded? (have no internet connection on that desktop computer).

After this small success I will keep on reading in a several new books on VHDL I got,  as it is the most interesting and unique programming language that exists! Unique for its superfast parallel programming results and its ability to make (digital) hardware in software by using plain text.

Hope this helps other Quartus students to start with simulating their designs.

AvB.

AVanB3
Beginner
174 Views

Just in case other Quartus starters need it here in short explained how to make a graphical Testbench vwf Vector Wave bench test file:

After the Entity successful is compiled, a graphical Wave Testbench vwf File can be made for simulating the Entity.

Go to FILE => NEW and select Verification/Debugging Files =>
University Program VWF.

In the opening "Simulation Waveform Editor" window select EDIT => Insert Node... and add all in - and output ports of your Entity to be tested.

And Edit with the mousecursor all waves to the desired values '1', '0', 'Z' or 'X'.

If the Testbench Waves are ready Save that .vwf File with the same name as your Entity circuit.

There this Wave file can always be found for Simulation of the Entity under test. Just select OPEN in the "Simulation Waveform Editor window" and select the premade Graphical Testbench 'entity_name.vwf' file and after that => SIMULATION => Run functional Simulation, or Run Timing Simulation. And this will show a new Testbench Vector Wave window with all Simulation results after the Simulation is finished.

AvB

 

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