Quartus Prime Avalon SDRAM Controller - readdatavalid never asserting

[albertsun]

I'm currently using the DE2-115 education board and implementing the SDRAM controller. When instantiating a read (from the Avalon MM documentation, I believe read requests are pipelined), the readdatavalid signal from the controller is never asserted even when read is asserted. I have tried both leaving the address and read asserted, and de-asserting the read signal after one clock cycle. I believe all the controller ports are connected properly, but I can't be 100% sure since I don't have access to a simulator. Thanks to everyone in advance.

[AdzimZM_Intel]

Hi Sir,

Do you see the waitrequest signal has been asserted after the read signal been asserted?

Do you see any difference when using burst operation?

I can assist you on Simulator (Modelsim) to simulate the design if you want.

But I need the design file and maybe some instructions.

Thanks,

Adzim

[AdzimZM_Intel]

Hello,

I'm hope you're doing well.

May I have any update on this case?

Thanks,

Adzim

[albertsun]

Hello,

Apologies for taking awhile to respond. Since the time of posting, I've transitioned to using M9K blocks instead for memory since the application doesn't have a high memory capacity requirement. I've attached a relevant snippet from my wrapper around the SDRAM controller - if that looks good, then there might've been some stray X's within a few signals.

Thanks for all the help again.

[AdzimZM_Intel]

Hello,

I'm glad to hear from you. Thanks for your update.

I think the wrapper looks okay.

Please let me know if you have further question on this topic.

Thanks,

Adzim

[AdzimZM_Intel]

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