Quartus SDC file: how to specify a register source for a multi path statement ?

[MNeum14]

I have a larger hirachical design, under the help from the 'technology Map Viewer' I created

(the following command in a single line) >>

set_multicycle_path -nocase -from [get_registers {la_control:la_control_1|rg_*}] -rise_to [get_clocks {pll_60_100_200MHz:Pll_1|altpll:altpll_component|_clk1}] 3

the result

Error (332000): invalid command name "get_parents_location" while executing

"unknown_original get_parents_location" ...

I am fighting the 2nd day, tried get_nets , optipon -nocase and and and. I am realla stucked. And I have to fix this problem. What are I doing wrong??

[sstrell]

The error doesn't seem to match or apply to the SDC command you've posted. When do you see this error? Compiling the design or running timing analysis?

The multicycle command itself looks fine to me, though you probably need to add a -setup or -hold to it depending on which analysis you're applying the multicycle to.

#iwork4intel

[MNeum14]

thanks for the response. I get this error when I compile the design and this error is related to this single line, whenever I comment this one out, everything is fine (however timequest reports time violations). I expect a stupid syntay error - but what I am doing wrong?

And yes, I agree, the multicycle command needs to get improved - but first I have solve this error...

[MNeum14]

the problem is within >>-from [get_registers {la_control:la_control_1|rg_*}]<<

I replaced it for a test with a top_level signal >>-from [get_registers {mem_wr_p*}] << and it works Ok

to summarize the involved File structure:

Top entity file               LA_FPGA.vhd

there instantiated       la_control_1 : ENTITY work.la_control

file                           la_control.vhd

with registers               rg_ch_select

(candidates for            rg_trg_mode

 multicycle)                  rg_clk_cntl

                               rg_status_1     

                               rg_status_2     

                               rg_trg_cntl     

                               rg_trg_ref      

                               rg_trg_snapshot 

                               rg_trg_state    

[MNeum14]

In the Quartus Netlist Viewer I see such a register as >>  |La_FPGA|la_control:la_control_1|la_clock:la_clock_1|rg_clk_cntl[26]

[MNeum14]

ooops, in the previous post I picked a wrong example, a correct one is

|La_FPGA|la_control:la_control_1|rg_ch_select[15]

[MNeum14]

Problem solved with the TimeQuest Tool

I was not aware that the Timequest Timing AlalyzerTool offers sdc file reneration including constraints settins. What did I wrong ? - hard to tell, the working result however is

set_multicycle_path -setup -end -from [get_registers -nocase {la_control:la_control_1|rg_*}] -to [get_clocks {pll_60_100_200MHz:Pll_1|altpll:altpll_component|_clk1}] 3

-nocase seems to be on the wrong spot ...

[KhaiChein_Y_Intel]

Hi,

Thanks for the update. I believe your update is beneficial to other users who have the same problem.

Thanks.