Hi guys,
I have little example code:
A generic package:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package test_pkg is
generic(
N : positive := 20
);
type t_arr is array(natural range <>) of std_logic_vector(N-1 downto 0);
type t_rec is record
data : t_arr(0 to 3);
end record;
end test_pkg;
package body test_pkg is
end test_pkg;A instance of the generic package:
library ieee;
package test10_pkg is new work.test_pkg
generic map (
N => 10
);And a rtl-testbench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test10_pkg.all;
entity tb is
port(
test1_in : in t_rec;
test1_out1 : out t_rec;
test1_out2 : out t_arr(0 to 3);
test1_out3 : out std_logic_vector(9 downto 0);
test1_out4 : out std_logic;
test1_out5 : out std_logic_vector(1 downto 0)
);
end tb;
architecture rtl of tb is
begin
test1_out1 <= test1_in;
test1_out2 <= test1_in.data;
test1_out3 <= test1_in.data(0);
test1_out4 <= test1_in.data(1)(5);
test1_out5 <= test1_in.data(1)(3 downto 2);
end rtl;And a screenshot of the RTL:
Can some explain why the outputs 4 and 5 are not connected in the RTL?
Best Regards
Oliver
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