I've got a problem that Quartus prime sythesizes away to much of my design.
I've got a 20 bit buffer in my design and when I try to sythesize it, quartus truncates this buffer to a 19 bit buffer, although I'm using the full 20 bit range of it.
I really cant explain, why he's doing it and I hope s.o. can help me with that issue or maybe how I can tell quartus to not optimize specific logic.
Quartus Version: 19.1
FPGA: Cyclone 10 GX
I would first say if Quartus is optimizing out some of your logic it really is because it is superfluous. You have registers/logic that goes nowhere so Quartus can safely discard it.
That being said, there are attributes you can attach to registers or wires that say to preserve them, even if they would be optimized away. Search for 'preserve_signal' attribute in the Quartus manual.