RAM block failing timing at 320Mhz

[SAbde7]

I am using the DE5-net kit(Stratix V). There is a RAM block in my design that is being clocked with 400 Mhz(only as a test. I actually want to go higher). Paths inside the RAM block (between porta_we_reg 's) fail timing even if I lower the frequency down to 320 MHz . TimeQuest says it's a long combinational path. Is 400 Mhz too much for the IP to handle or do I need to do something in the timing constraints/IP parameters?

[sstrell]

Can you post your .sdc, the detailed timing report and perhaps the code implementing the memory?

That's pretty fast for a Stratix V design.

#iwork4intel

[Kenny_Tan]

Any update?

[SAbde7]

It turns out the failing path was not internal but a loop through outside logic back to an internal register. It was hard to tell from the source and destination registers(their names are misleading). I have added constraints to the project to try to target this path and it seems to be working with over 400 MHz now, though I get other strange timing failures for other paths when I try to go higher, which I will probably ask about in another thread.