Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15378 Discussions

Reading inputs in a state-machine

AIbra11
Beginner
148 Views

Hello, 
I've spent a lot of time trying to get this state machine working with no hope.

 

Requirement: In this FSM, we want to set:

- opcode_reg and offset_reg to USB3_DATA(3 downto 0) and USB_DATA(15 downto 4) respectively in GET_OPCODE_OFFSET state (and keep its value after that)

- RegLengthCounter to unsigned(USB3_DATA(11 downto 0)), and RegPointer to unsigned(OffsetReg) in GET_LENGTH state. (and keep its value after that)

 

Here is the code I've written so far (attached), specifically processes:

USB_CLK_PROC and RegProxy_FSM_Proc

 

Problem:

- The data is registered correctly, but changes at the next clock edge, how can I keep it fixed?

0 Kudos
2 Replies
sstrell
Honored Contributor III
130 Views

Follow the LHS (left hand side)!

Are you sure USB3_DATA isn't changing at all?  You have it in a separate assignment (non-clocked logic), so it will update immediately if there is a change:

USB3_DATA <= USBSendDataOut when USBWrOeRSig = '1' else (others => 'Z');

AIbra11
Beginner
117 Views

Thank you, it was a timing issue, I was wrongly sampling the data at the same edge when it changes.

Changed sampling moment to be on the opposite clock edge.

Reply