Reduce oscillator frequency

[Altera_Forum]

Hi, 

I have timing problems in Quartus and got suggested to reduce my oscillator frequency. Is this possible through Quartus? I'm using a DE0-boards, Cycylone III.  Thanks a lot.  Regards, mr_embedded

[Altera_Forum]

The DE0 has a 50MHz oscillator built in. If this is too high you could create a clock divider circuit in HDL or use a PLL from the Altera MegaCore package that comes with Quartus.

[Altera_Forum]

Thank you, 

I guess there is no simple solution like clicking a CLOCK DIVIDE BY 2 or something in Quartus.  // mr_embedded

[Altera_Forum]

employ megawizard pll primitive

[Altera_Forum]

what is that? A module in SOPC-builder?

[Altera_Forum]

--- Quote Start ---  employ megawizard pll primitive  --- Quote End ---    The Altera DE2 has on-board 27 MHz and 50 MHz physical oscillators. Using the ALTPLL (or just the PLL), I can divide to the minimum clock frequency of 9.375 MHz (although the claimed minimum is 10 MHz). My question is how can I get a 5 MHz frequency? I know I can use an external clock through the SMA connector, but is there an on-board solution to solve this problem?  thanks.   Jack

[Altera_Forum]

You can keep a 10MHz clock and use a clock enable signal that is only active on half the cycles.

[Altera_Forum]

what should be driving the clock enable signal physically?

[Altera_Forum]

your logic e.g. 

 clked process... enable <= not enable;