Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Reducing timing for critical path, Adding pipeline registers not working.




I'm trying to optimize a part of my design to meet my timing goal (150 MHz ~6.66ns path) but one register is not being read as a register on my timing analysis and I don't know why. In the timing analyzer it shows the register cell as a logical cell in the middle of the path, however, since it is a register, it should be at the end of the path.


My design has 2-stages (i.e. pipelined), at least it is supposed to be but the analyzer is not reading the variable as a register.


Here is the code snippet in question:

always_ff @(posedge clk) begin if (rst) begin for (int i = 0; i < 6; i++) read_mux_out_reg[i] <= 0; end else begin for (int i = 0; i < 6; i++) read_mux_out_reg[i] <= read_mux_out[i]; end end

Here is the critical path shown in timing analyzer:




Is there something I need to be doing in the timing analyzer for this to work? Any help is greatly appreciated, I've been stuck on this for a while and I've tried a bunch of things to synthesize a register but none of the I tried change the result of the timing analyzer.


Thank you~

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Well, I figured out my problem. It is because there was a lot of mux concatenation from my arrays to the output (This is because I read combinationaly). I simply added another pipeline stage to compensate and now I am meeting my timing requirements.

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