start clock and end clock sounds more like a simulator than static timing analysis, but I may not understand the question. Clocks are usually controlled by:
create_clock -period 10.0 -name clk_name [get_ports clk_name]
Internally they are constrained with derive_pll_clocks. I would recommend the following(I wrote it, so biased) for getting started:
http://www.alterawiki.com/wiki/timequest_user_guide
