SIGSEGV in ModelSim 10.0c

[Altera_Forum]

I get the following error doing RTL simulation in ModelSim 

  --- Quote Start ---  # Loading work.ple(a) # ** Fatal: (SIGSEGV) Bad handle or reference. # Time: 0 ps Iteration: 0 Process: /iddreaderbinning_vhd_tst/i1/line__195 File: C:/qdesigns/c-cam/cameras/sensor/cmosis/cmvremap/cmvremapbinning/iddreaderbinning/iddreaderbinning.vhd # FATAL ERROR while loading design # Error loading design   --- Quote End ---   The offending line is in bold:  begin process(Clk, Reset) is begin if Reset = '1' then oddline <= '0'; Q <= (others => '0') ; muxsel <= 0 ; elsif rising_edge(Clk) then if (StartOfFrame = '1') or (EndOfLine = '1') then oddline <= (not StartOfFrame) and (not oddline) ; end if; if (pl_Ena(0) = '1') then Q <= subvector( std_logic_vector( to_unsigned( ( to_integer( unsigned( subvector(ramreader_Q , WIDTH_D * 1 - 1 , WIDTH_D * 0 ))) + to_integer( unsigned( subvector(ramreader_Q , WIDTH_D * 2 - 1 , WIDTH_D * 1 )))) + ( to_integer( unsigned( subvector(ramreader_Q , WIDTH_D * 3 - 1 , WIDTH_D * 2 ))) + to_integer( unsigned( subvector(ramreader_Q , WIDTH_D * 4 - 1 , WIDTH_D * 3 )))) , WIDTH_D + 2)) , WIDTH_D + 2 - 1 , WIDTH_D - WIDTH_Q + 2 ) ; end if ; muxsel <= to_integer( unsigned( subvector( ramreader_A , ADDRESS_WIDTH , ADDRESS_WIDTH - 1 ))) ; end if; end process ; process(EndOfLine , oddline , YHeight , D , rowcounter_Q , ramreader_A , muxeven_Q , muxodd_Q , ramreader_EoP , ramreader_RdAvail , pl_WrFree) variable rowcounterqslv : std_logic_vector(WIDTH_ROWCOUNT - 1 downto 0) ; begin ramreaderstartp <= EndOfLine and oddline; rowcountermax <= to_integer( unsigned( YHeight)) ; muxevend <= subset_stdlogic_2D( D , 3 , 0 ) ; muxoddd <= subset_stdlogic_2D( D , 7 , 4 ) ; rowcounterqslv := std_logic_vector( to_unsigned( rowcounter_Q , WIDTH_ROWCOUNT )) ; A <= combine_slv( rowcounterqslv(0) , subvector(ramreader_A , ADDRESS_WIDTH - 2 , 0)) ; ramreaderdata <= combine_slv( muxodd_Q , muxeven_Q ) ; rowcountercnten <= ramreader_EoP and ramreader_RdAvail and pl_WrFree ; end process; rowcounter : upcounter generic map( Any suggestions ?

[Altera_Forum]

I've seen SIGSEGV errors 'cured' by using the -novopt option ... see if that helps. 

 You could also try a different combo of Quartus+Modelsim to see if this is a new error.  Cheers, Dave

[Altera_Forum]

SIGSEGV is a segmentation violation and a modelsim crash, nothing wrong with your code neccesarily. I suggest reporting the problem to mentor.

[Altera_Forum]

--- Quote Start ---  SIGSEGV is a segmentation violation and a modelsim crash, nothing wrong with your code neccesarily. I suggest reporting the problem to mentor.  --- Quote End ---   I don't think Mentor will be of great help ... I searched their web-site (Dave Howard pointed me to it), even registered, but didn't get far. Reporting a problem is well hidden, sending a 'don't bother, we are not interested' message.  I guess I could try Timing simulation, but that runs rather slow, and I have to encapsulate the actual code in a bigger project, which I 'll have to simulate as well, so getting rid of this SIGSEGV error would be great. I'll try Dave's suggestion first. It may have a problem with some of my functions. I'll use the binary cut and search approach to see where it goes wrong.

[Altera_Forum]

--- Quote Start ---  I don't think Mentor will be of great help ...   --- Quote End ---    I find their support is excellent.  Do you have a full edition of Modelsim? If you can reproduce the issue with a smaller design and post it (or email it to me), I'll confirm it fails under a few different tool versions, and submit it under my mentor site ID.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  I find their support is excellent.  Do you have a full edition of Modelsim? If you can reproduce the issue with a smaller design and post it (or email it to me), I'll confirm it fails under a few different tool versions, and submit it under my mentor site ID.  Cheers, Dave  --- Quote End ---    There is a small (I'd say big) difference: I'm a lowly cheapskate using the Altera Starter Edition and you are a professor ... and to big EDA companies that matters. I'll send you a .qar via private mail.  Thanks,  Josy

[Altera_Forum]

--- Quote Start ---  I find their support is excellent.  Do you have a full edition of Modelsim? If you can reproduce the issue with a smaller design and post it (or email it to me), I'll confirm it fails under a few different tool versions, and submit it under my mentor site ID.  Cheers, Dave  --- Quote End ---    Ditto. Ive reported several things that have been fixed. Their issue tracking is much better than Altera's; they keep Enhancement requests and defect reports open until the issues are added or fixed. Altera just say "Thanks, we'll close this now".

[Altera_Forum]

Hi all, 

 I managed to get a bit further. The problem was actually in the .vht file. I use the testbench writer to generate the .vht testbench which I then modify heavily (as it sucks when I have used a std_logic_2D type (from the lpm-package)). I now also tried using generics to control the simulation for different input and output widths and I messed it up. As now the SIGSEGV error is gone, all I have to do is to weed out the other errors. To Tricky: I also got a few evasive 'We will close the SR now' ... so I don't bother any more. And they don't even seem to mind that we complain about on their forum. How come? I guess they are not interested in the 80% that only generates the 20% of income?  But most often the error is in our code. I just got overwhelmed with that SIGSEGV error., so I called out for help, maybe a bit quick. But then again, it was Sunday night 9:00 pm ...  Thank you all for the help!  Josy

[Altera_Forum]

--- Quote Start ---    But most often the error is in our code. I just got overwhelmed with that SIGSEGV error.,    --- Quote End ---    True, but no code should cause a segmentation fault - thats a bug in modelsim (and there are plenty, especially when you use the little used parts of VHDL).  The worse ones are the crash to desktop with no error message, and the problem is somewhere in your 5000 line package!!

[Altera_Forum]

--- Quote Start ---  I'm a lowly cheapskate using the Altera Starter Edition and you are a professor ... and to big EDA companies that matters.   --- Quote End ---    Nah, I'm just a lowly cheapskate that qualifies for Mentor University Program pricing :)  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  True, but no code should cause a segmentation fault - thats a bug in modelsim (and there are plenty, especially when you use the little used parts of VHDL).  --- Quote End ---    Can I take that as a compliment? ;)  I did send my code to Dave, I leave it up to him to poke Mentor ...