Signal Tap - Instance not found

[jlats2]

Hello,

Thank you for reading my post. I am having some issues using signal tap. Whenever I program my fpga with  a new SOF, the signaltap tool states 'instance not found' and it asks me to re-program the SOF.  I am not sure what is causing this but it is preventing me from using the logic analyzer (I can program the fpga, I just can't view my signals).

Based on some research, this is what I have tried so far and none of this has worked. I was hoping that someone might be able to help point me in the right direction.

Things I have tried:

1)  I removed the signal tap file (deleted it) and created a new one. Re-compiled and signal tap still states 'instance not found' after loading.

2)  After compilation with signal tap, I used timequest to make a basic SDC file. I do not have any timing issues in this design (all signal tap signals meet timing).

3) I cleaned the quartus project, and recompiled everything, still having the same issue.

4) I checked the compilation report synthesis >  in-system-debug and checked the signals.  some are unconnected but most (inducing the clock signal) are connected.

I have successfully used signal tap on this design before, but now it is not working.

Quartus pro 18.1, Cyclone 10 GX

Thank you for your help,

James

[sstrell]

Double-check that you've actually enabled Signal Tap in the Settings dialog box.  You may have the .stp file but if that checkbox is not enabled, the logic analyzer won't get included in the design.  I'm presuming you're using the usual .stp file flow and not manually instantiating Signal Tap into the design.

In the project hierarchy, do you see the Signal Tap and related IP (like sld_hub or auto_fab) included in the project?  If not, this is a clear indicator that it's not been added.

Are you adding pre-synthesis or post-fit nodes to the logic analyzer? 

What hardware connection are you using to your device?  I presume a USB Blaster, but confirm that you're using the same JTAG connection for successful programming as what you're using for Signal Tap.

[jlats2]

Thank you for your reply.

I am using a 'USB blaster' which is the same JTAG connection I use to program the FPGA.

I am adding pre-synthesis nodes.

I did not have signaltap enabled. I deleted all of my old stp files and created a new one. I added it to the project and can see it listed among my other files. Then, I went into assignments > settings > and clicked on the 'enable signal tap logic analyzer' and made sure that my new signal tap file (stp_test.stp) was selected. I compile the project (once) and then went back and used timequest to refresh my sdc file. I then compile the project again. Unfortunately, I still receive the 'instnace not found' message when I attempt to use signal tap.

Also, I do not see auto_fab or sld_hub IP included in my project files (if I search the messages I see reference to these files but they are not included in my project). Should I include the autofab  somehow?

Best Regards,

James

[jlats2]

Looking into this further, I believe the issue is that I have don't have the auto_fab megafunctions referenced in my project. I must have accidentally deleted them (as I was able to use signaltap in the past).

How can I add these back into the project? It appears that singaltap does this once whenever the first stp is added, but it does not appear to include the auto_fab IP if it has been deleted.

Any thoughts?

Thank you again for all of your help,

James

[sstrell]

Recompiling should have recreated those.  However, the best thing to do now would be to just recompile from scratch.

Close the project, delete the qdb folder, and recompile.

[jlats2]

Thank you for your reply.

I deleted and reinstalled quartus pro 18.1 and then deleted the qdp folder and recompiled. I can now used Signaltap.

Thank you very much for your help in resolving this issue

For future readers that have this problem try the following:

1) ensure that you have a basic timequest SDC file: https://people.ece.cornell.edu/land/courses/ece5760/Quartus/TimeQuest_sdc_file.html

2) recompile with the new SDC file added to the project and ensure that there are no timing issues (especially with signal tap clocks)

3) If the above does not work, close quartus and the project, delete the 'qdp' folder. then re-open and recompile.

4) if this still does not work, uninstall and reinstall quartus (not as messy as you might think), remove the qdp folder, then re-compile.

I hope this helps future users.

Best Regards,

James

[sstrell]

That's the qdb folder, not qdp.

[SyafieqS]

Thanks James for the sharing. Since the issue had been resolved, I will put this to close pending.