Hi i am working with DE1-SoC Cyclone V SoC FPGA Board and i am using quartus Prime Lite Edition. I am trying to use Signal Tap Logic Analyzer II but somehow i am not able to configure it correctly my trigger condition get triggered successfully but the data log in the logic analyzer is just the last value rather than all the previous values occur before trigger condition. What can be possible thing i am missing. Any guide on this topic will be very helpful.
thanks in advance
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What do you have the trigger position in the .stp file set to? If you want to see more captured data from before the trigger occurs (to the right of the trigger in the waveform view), set it to the post-trigger position.
However, none of the 3 trigger position options would only show a single value unless either your signals are not toggling around the time of the trigger or you've set the size of the buffer incorrectly (only 1 sample perhaps?).
Also, of course, your sampling clock has to toggle so data gets captured at each rising edge.
Hi,
I have attached the snap of all the configuration set in my stp file. I have also tried all 3 different position but non of them work.
Hi,
Make sure you're using non-segmented buffer in continuous mode instead of non-segmented buffer using a storage qualifier and segmented buffer. In the continuous data capture, Trig1 occurs several times in the data buffer before the Signal Tap logic analyzer trigger activates. The buffer must be full before the logic analyzer evaluates any trigger condition.
Thanks,
Best Regards,
Sheng
My logic is i have implemented a simple counter which count from zero and count till 15. Once it reach 15 it enable the stop bit which should act a trigger to stop my acquisition. As the FPGA clock is of 50MHZ so to slow down the count i have used clock divider which generate a clock of 1 Hz and my counter is updating on every posedge of the 1 Hz clock. I am trying to see all the values of my counter on Signal Tap which i am unable to see.
CLOCK_50 should not be in the node list. You already have that as the capture clock. I think perhaps you mean to put the 1Hz clock as the capture clock and have CLOCK_50 in the node list, but then the capture clock would be way too slow to capture CLOCK_50. So simply have the 1Hz clock as the capture clock and remove CLOCK_50 from the node list. With CLOCK_50 as the sampling clock, you're filling up the buffer long before there's even one cycle of the counter.
You also don't need the trigger in. Disable that.
Yes regarding the clock you are right. I was also thinking the same that may be my buffer is getting overwrite with 50 Mhz clock thats why i am only able to see one sample.
But disabling the trigger in so how the data acquisition will stop as i dont want any extra samples
As the reason i am testing trigger in because i want to run a C program on one of my design which have to stop after a particular condition is match or if all the lines of the code is executed. I dont want to stop sampling before that and i also dont want samples after that
You already have stop in the node list as your trigger. Trigger in is only used to get a trigger from another instance of the logic analyzer or from some other external signal that you're not tapping in the node list. You don't need to use it here.
ok as you said that as i have stop signal in my node list so i dont have to used it as trigger in. What if remove it from node list and only use it as trigger in so will that stop the acquisition as soon as stop value gets to 1?
I mean i am just trying to understand that how it is working as i cant always make sure that the program i am running will be complete in 64 samples or it will take more than that so isnt there any way to set up such a configuration which works as per my design requirements
ok thanks for clearing my doubts. I will get back to you if i have any more queries.
