Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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SignalTapII for continuous data acquisition ?

hucklord
Beginner
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I'm looking for a method to store all data from a 16 bit register on my FPGA. I'm currently using Signaltap to view data in real time using the "Autorun Analysis", and save the data logs for each trigger individually to a csv or list file - how can I save the entire length of the analysis to a single file?

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hucklord
Beginner
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To update on my progress:

I have gotten the Matlab MEX connection to work, which allows me to sample my data in real-time, but it's painfully slow (~5 samples/sec) compared to the rate that the SignalTap data logs are being made (74k samples/sec). Ideally I would just be able to save all of these data logs to a single file, for further analysis.

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sstrell
Honored Contributor III
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How much data are we talking about?  You could make use of a segmented buffer and/or storage qualification to collect all the data you need in a single run depending on how much it is and if it can be qualified.

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hucklord
Beginner
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HI, thanks for your response. The total amount of data will be > 100MB, so I don't think I could collect it all in one run. What I did try, was to use matlab mex to sample the data in groups of 16k samples, but even then it could not keep up to my sampling rate. It seems ridiculous that there isn't a way to save multiple data logs at once?

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Nurina
Employee
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Hi,


Did the above reply help?




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hucklord
Beginner
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Not really. Could you answer my question: Can I save multiple data logs at once?

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sstrell
Honored Contributor III
642 Views

No, this isn't possible.  You can't capture this much data inside the FPGA (limited buffer space) and as you've already found, sampling over the 24 MHz interface of JTAG is not sufficient.  It might be better to look at the logic analyzer interface (LAI) to send the signals you want to see outside the device to a bench logic analyzer and use the huge storage available there.

Or you could look at a state-based trigger to have full control over how much buffer space each trigger stores in a segmented buffer to make most efficient use of the on-chip buffer.  

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hucklord
Beginner
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I'm pretty sure that's what I'm trying to do. I can send the signals to the LAI, and I could export them to a csv one at a time, but I'm trying to find a way to export them all at once. It seems like a trivial thing to do, but I can't figure it out! I attached an image of the interface after I've run an analysis.

 

Thanks for the help.

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sstrell
Honored Contributor III
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No, the LAI is a separate debugging feature of Quartus (not Signal Tap).  You use unused pins on your FPGA to send internal signals out of the device to a bench logic analyzer or other bench lab equipment.  See the Debug Tools user guide:

 

https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/user-guides.html

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Nurina
Employee
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