I want to run a simulation on a custom IP for Altera (using quartus) . While creating IP, Quartus provides an option to generate simulation files along with IP. However, on enabling that option, quartus errors out while generating IP
"Error: <custom IP> does not support generation for Verilog Simulation. Generation is available for: Quartus Synthesis.
Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings
Error: SPD file was not generated:
Error: Could not generate simulation scripts
Any pointer on this will be appreciated.
I will be happy to provide any further information on this.
Thanks in advance.
More detail definitely needed here. I'm guessing this is a custom component in Platform Designer because of "qsys-generate." Are you saying you used the Component Editor and added simulation-specific files on the Files tab and then trying to generate the system for simulation?
Hi @sstrell ,
Thanks a lot for the reply.
I am trying to generate the simulation model for the custom component. Actually, I am a beginner in the Quartus world.
This is what I did.
I have <*>_hw.tcl, along with the corresponding RTL for which I need to generate the IP. According to Quartus documentation, If I open the Quartus GUI in same directory in which these files are kept, it will automatically detect the IP, and I can continue onto the parameter editor, followed by "Generate HDL" in order to generate the IP variation. Now, just before hitting the "Generate HDL" option, I selected "Verilog" for simulation model, which resulted in error "<IP> doesnot support generation for verilog simulation. Generation is available for : Quartus synthesis".
Do I need to provide additional simulation files for it? AFAIK, Quartus should generate those for me.
You have a hw.tcl file so that means the Component Editor in Platform Designer was used to create it. It sounds like only files were added for the component for synthesis, not simulation.
In the IP Catalog in Platform Designer, right-click the component and select Edit. This will reopen the Component Editor. On the Files tab, add simulation-only file(s) to the Verilog or VHDL simulation section, or click the button to copy the synthesis files to the simulation files list. Click Finish to regenerate the hw.tcl file. You should now be able to perform a generation for the simulation.