Here's the error message:
Error (275021): Illegal wire or bus name "mif_select[7:0]" of type port
Error (275021): Illegal wire or bus name "counter[2:0]" of type port
Error (12152): Can't elaborate user hierarchy "Down_Counter_Clock_Select:inst100"
Error: Quartus II 64-Bit Analysis & Elaboration was unsuccessful. 3 errors, 3 warnings
Error: Peak virtual memory: 4672 megabytes
Error: Processing ended: Thu Sep 02 14:51:28 2021
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:03
And here's the HDL code generated by the State Machine Wizard:
-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- Created on Wed Sep 01 14:28:57 2021
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ROM_Select_State_Machine IS
PORT (
reset : IN STD_LOGIC := '0';
clock : IN STD_LOGIC;
mif_select : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
busy : IN STD_LOGIC := '0';
counter : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
mif_select_changed : IN STD_LOGIC := '0';
write_from_rom : OUT STD_LOGIC;
reconfig : OUT STD_LOGIC;
enable_counter : OUT STD_LOGIC;
clear_counter : OUT STD_LOGIC
);
END ROM_Select_State_Machine;
ARCHITECTURE BEHAVIOR OF ROM_Select_State_Machine IS
TYPE type_fstate IS (state1,state2,state3,state4,state5,state6,state7,state8,state9);
SIGNAL fstate : type_fstate;
SIGNAL reg_fstate : type_fstate;
BEGIN
PROCESS (clock,reg_fstate)
BEGIN
IF (clock='1' AND clock'event) THEN
fstate <= reg_fstate;
END IF;
END PROCESS;
PROCESS (fstate,reset,mif_select,busy,counter,mif_select_changed)
BEGIN
IF (reset='1') THEN
reg_fstate <= state1;
write_from_rom <= '0';
reconfig <= '0';
enable_counter <= '0';
clear_counter <= '0';
ELSE
write_from_rom <= '0';
reconfig <= '0';
enable_counter <= '0';
clear_counter <= '0';
CASE fstate IS
WHEN state1 =>
IF ((mif_select(7 DOWNTO 0) /= "00000000")) THEN
reg_fstate <= state2;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= state1;
END IF;
enable_counter <= '0';
clear_counter <= '0';
reconfig <= '0';
write_from_rom <= '0';
WHEN state2 =>
IF (NOT((busy = '1'))) THEN
reg_fstate <= state3;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= state2;
END IF;
enable_counter <= '0';
clear_counter <= '0';
reconfig <= '0';
write_from_rom <= '0';
WHEN state3 =>
IF ((counter(2 DOWNTO 0) = "001")) THEN
reg_fstate <= state4;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= state3;
END IF;
enable_counter <= '1';
clear_counter <= '0';
reconfig <= '0';
write_from_rom <= '0';
WHEN state4 =>
IF ((counter(2 DOWNTO 0) = "010")) THEN
reg_fstate <= state5;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= state4;
END IF;
enable_counter <= '1';
clear_counter <= '0';
reconfig <= '0';
write_from_rom <= '1';
WHEN state5 =>
IF ((busy = '1')) THEN
reg_fstate <= state6;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= state5;
END IF;
enable_counter <= '0';
clear_counter <= '0';
reconfig <= '0';
write_from_rom <= '0';
WHEN state6 =>
IF (NOT((busy = '1'))) THEN
reg_fstate <= state7;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= state6;
END IF;
enable_counter <= '0';
clear_counter <= '0';
reconfig <= '0';
write_from_rom <= '0';
WHEN state7 =>
IF ((counter(2 DOWNTO 0) = "011")) THEN
reg_fstate <= state8;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= state7;
END IF;
enable_counter <= '1';
clear_counter <= '0';
reconfig <= '0';
write_from_rom <= '0';
WHEN state8 =>
IF ((counter(2 DOWNTO 0) = "100")) THEN
reg_fstate <= state9;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= state8;
END IF;
enable_counter <= '1';
clear_counter <= '0';
reconfig <= '1';
write_from_rom <= '0';
WHEN state9 =>
IF ((mif_select_changed = '1')) THEN
reg_fstate <= state2;
-- Inserting 'else' block to prevent latch inference
ELSE
reg_fstate <= state9;
END IF;
enable_counter <= '0';
clear_counter <= '1';
reconfig <= '0';
write_from_rom <= '0';
WHEN OTHERS =>
write_from_rom <= 'X';
reconfig <= 'X';
enable_counter <= 'X';
clear_counter <= 'X';
report "Reach undefined state";
END CASE;
END IF;
END PROCESS;
END BEHAVIOR;
Thanks for any help you could provide.
