Synthesizing Signed Multipliers

[Altera_Forum]

Hi All, 

I am trying to synthesize an FIR in quartus II. But I have problem in synthesizing a signed multiplier. My multiplier code is given below.  The problem is for each multiplier Quartus II substitute an lpm_mult from the library but it is substituting an UNSIGNED verision.   I checked the lpm_mult.tdf file and the parameter is assigned as LPM_REPRESENTATION = "UNSIGNED". This is a read-only file so I cant change it.  Anyone knows how to force Quartus to synthesize it with a signed multiplier????  //--- pipelined multipliers for FPGAs --- reg signed [35:0] mult_res_p0_1; reg signed [35:0] mult_res_1; reg signed [17:0] mult_ina_1; reg signed [17:0] mult_inb_1; always @(posedge clk) begin  if (enable==1'b1)  begin  mult_ina_1 <= parDataDelayLine_dly_1;  mult_inb_1 <= parCoefDelayLine_dly_1;  mult_res_p0_1 <= mult_ina_1 * mult_inb_1;  mult_res_1 <= mult_res_p0_1;  end end

[Altera_Forum]

Instantiate your own lpm_mult is probably the easiest solution, rather than using *

[Altera_Forum]

--- Quote Start ---  The problem is for each multiplier Quartus II substitute an lpm_mult from the library but it is substituting an UNSIGNED verision.   I checked the lpm_mult.tdf file and the parameter is assigned as LPM_REPRESENTATION = "UNSIGNED".  --- Quote End ---     I did not try your code, but I did try the Signed Multiply VHDL template. I think you were looking at the parameter default in the .tdf file. I had an unsigned default there, but the "LPM Parameter Settings --> Multipliers --> lpm_mult Parameter Settings by Entity Instance" table in the Analysis & Synthesis compilation report had SIGNED for LPM_REPRESENTATION.

[Altera_Forum]

My bad. Thank you. Indeed I was looking at the default settings. Thank you guys