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SystemVerilog Error

Petrov1
Novice
237 Views

Hello guys, I received error: Error (12061): Can't synthesize current design -- Top partition does not contain any logic.

I am trying to test a verilog module in system verilog. Can anyone please help me with it.

The code: 

module test_validin();
reg din1;
reg clk1;
reg res1;
wire out1;


valid_in test_validin1(.din(din1),
.clk(clk1),
.res(res1),
.out(out1));

always #10 clk1<=~clk1;

initial begin
res1 <= 0;
din1 <= 0;

#10 res1 <= 1;
#5 din1 <= 1;
#8 din1 <= 0;
#2 din1 <= 1;
#10 din1 <= 0;
end

always @(posedge clk1) begin
#25
din1 = 0;
#27
if (out1 != 1)
$display ("Error");
#200
din1 = 1;
end
endmodule

0 Kudos
1 Solution
sstrell
Honored Contributor III
217 Views

This looks like a simulation testbench so at least some of it (most of it actually) would not be synthesizable (initial block, delays, $display, etc.).

But if you have synthesizable designs with this error, make sure the .v or .sv file is added to the Quartus project, the name of the file matches the name of the module (test_validin.sv), and that the top-level entity selected in the project matches the name of the module (test_validin in this case).

View solution in original post

3 Replies
sstrell
Honored Contributor III
218 Views

This looks like a simulation testbench so at least some of it (most of it actually) would not be synthesizable (initial block, delays, $display, etc.).

But if you have synthesizable designs with this error, make sure the .v or .sv file is added to the Quartus project, the name of the file matches the name of the module (test_validin.sv), and that the top-level entity selected in the project matches the name of the module (test_validin in this case).

View solution in original post

SyafieqS_Intel
Moderator
204 Views

Hi Iliyan,


Any update?


Petrov1
Novice
184 Views

I've marked the first reply as a solution. Thank you very much !

Reply