The RTL netlist is not available error

[CosmoKramer]

I completed building fpga image. But when I tried to looking at timing path in rtl viewer, I get error that RTL netlist is not available. 

I did not set this option - Aggressive Compile Time  - as per this link:

https://www.intel.com/content/www/us/en/support/programmable/articles/000086719.html

how can I resolve this issue? Tool cant complete timing analysis without a netlist so it must be there. 

[sstrell]

So you performed a full compilation and you're getting an error that you can't view the design in the RTL Viewer?

If you manually just run synthesis instead of a full compilation, can you view the design in the RTL Viewer?  

Is this Standard or Pro?

[ShengN_Intel]

Any further update or concern?