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The Value of tx_pll_m_divider is invalid

Altera_Forum
Honored Contributor II
‎01-09-2017 02:22 PM
1,209 Views

Hi Everyone; 

 

I am trying to synthesise Altera's 10GBASE-R PHY IP but I get these three errors  

 

Error (272006): The chosen data rate or input clock frequency cannot be implemented. (The value of tx_pll_m_divider is invalid) 

Error (272006): The chosen data rate or input clock frequency cannot be implemented. (The value of rx_cru_m_divider is invalid) 

Error (287078): Assertion error: Valid clear box generator not found or Errors encountered during clear box generation 

 

 

Assuming that fixing the first two errors fixes the third as well, I did some research but couldn't resolve it. Altera's support website says you have to use the MegaWizard plug-in to generate the instantiation but it doesn't give any instantiation template. It generates a component declaration file which I am using for declaring the component. Been trying to go round this problem for some days now so any help will be highly appreciated. 

 

Thanks
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