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CBehr
Beginner
1,042 Views

TimeQuest: How do I eliminate the clock delay through a PLL from my timing budget for external IO?

I've got the following related constraints:

set_clock_groups -asynchronous -group {input_clk_40} \

-group {pll_output_clk_50|Frac_PLL(eg.)}

-group {pll_output_clk_50|divclk}

create_clock -name virt_clk_50 -period 20

set_output_delay -add_delay -max 0 -clock virt_clk_50 [get_ports {out}]

set_output_delay -add_delay -min 0 -clock virt_clk_50 [get_ports {out}]

 

When I report timing in TimeQuest, it includes a 6-7ns delay from {input_clk_40} to {pll_output_clk_50} as part of the data arrival path.

 

I've tried setting a false path from the input clock to the pll clock and vice versa. The only thing I've managed to do was move the additional clock delay back and forth between the Data Arrival Path and the Data Required Path.

 

I may shortly go insane. Please help. Thanks.

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6 Replies
sstrell
Honored Contributor II
104 Views

You should not be isolating the input clock from the PLL outputs like this. You don't need that set_clock_groups command at all, assuming Frac_PLL and divclk are synchronous to each other and coming from the same PLL. Use a compensation mode in the PLL IP parameters to compensate for clock path delay, including through the PLL.

 

Also, your set_output_delay values should not be 0. They should accurately reflect the maximum and minimum external delays to the "downstream" device to guarantee meeting that device's setup and hold timing requirements.

CBehr
Beginner
104 Views

Thanks, but that's no help.

 

This is an asynchronous device. There is no timing related to any clock. The timing is related from output to input and vice versa. I've searched on this and no-one seems to have a accepted solution to the async bus so I need the constraints to be simple.

 

Maybe I can make the question simpler: How do I constrain a range of delay from the clock input of a register to the output pad of a register without ? When I try, the tool misinterprets that as the delay from the input clock (which is unrelated to a single register in the entire hardware design) to the output pad. Same thing for pad to register input. Is there something I'm missing? I've been reading through Ryan Scoville's guide and I'm not seeing an answer.

 

If anybody else has dealt with this, any suggestions in the right direction would help.

 

Thanks again.

 

104 Views

Hi,

 

For clock path, you can either select a compensation mode (eg, normal mode) or set a phase shift. I could not understand the following. Can you elaborate?

 

How do I constrain a range of delay from the clock input of a register to the output pad of a register without ? When I try, the tool misinterprets that as the delay from the input clock (which is unrelated to a single register in the entire hardware design) to the output pad.

 

Thanks

CBehr
Beginner
104 Views

Maybe it's best if I use an example:

 

Assume a clock delay of 9ns from the originating clock to the registers.

 

I want the data path to be between 6 and 7 ns both from the register to the IO pad and from the IO pad to the register (bi-directional data).

 

From my experimentation, it looks like on the output, you add the clock and data paths for the max delay and subtract the clock path from the data path on the min delay, but it doesn't seem to work all the time and I have no idea what the tool is doing.

 

So my question is for the above example, how do i write the set_max/min_delay constraints for both the output and the input?

 

Thanks

 

 

CBehr
Beginner
104 Views

I did some more experimentation and came up with an example. Please check out the following post:

 

https://forums.intel.com/s/question/0D50P000046JFY7SAO/problem-using-setmindelay-between-quartus-and...

 

Probably answer there. Thanks.

 

104 Views

Sure. I will answer in the new thread

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