Timing Analyzer Inter-Path-Competition in Nios sub-system

[CWarr1]

I am trying to close out timing in my Arria-10 FPGA design, using Quartus Prime V19.1.0 pro edition.
I clicked on the link to "report timing closure recommendations" This opened Timing Analyzer which reports "Inter-path-Competition" with 18 paths affected

This is the first recommendation:

★★★★★
Duplicate the nodes specified in the details for the path from u0|nilm_nios|nios...ss_line_field[4]u0|nilm_nios|nios2_gen2_2|cpu|d_address_line_field[4] to u0|nilm_onchip_me...m_block1a30~reg0u0|nilm_onchip_memory|onchip_memory2_1|the_altsyncram|auto_generated|ram_block1a30~reg0
Issue: Inter-path Competition
From: u0|nilm_nios|nios2_gen2_2|cpu|d_address_line_field[4]
To: u0|nilm_onchip_memory|onchip_memory2_1|the_altsyncram|auto_generated|ram_block1a30~reg0
Timing Analysis: report timing
Nodes to duplicate:
u0|nilm_nios|nios2_gen2_2|cpu|d_address_line_field[4]
u0|mm_interconnect_0|router|reduce_nor_11
u0|nilm_onchip_memory|onchip_memory2_1|the_altsyncram|auto_generated|decode3|rtl~0
★★★★★

So the path that is affected is between my Nios processor (nilm_nios) and its associated onchip memory (nilm_onchip_memory)
Since both of these modules are created and connected within Platform Designer, I can not see how to duplicate the specified nodes.
Can anyone suggest how I might resolve this error?

Thanks!
Chris

[KhaiChein_Y_Intel]

Hi,

You may add the setting below in the qsf file to duplicate a register

set_instance_assignment -name DUPLICATE_REGISTER -to <register_name> <num_duplicates>

Thanks

Best regards,

KhaiY

[CWarr1]

Thanks.
My QSF file has a message:

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten

Is it OK to ignore this, or can I create a different QSF file?

Regards

[KhaiChein_Y_Intel]

Hi,

You may also duplicate the register using Manual Logic Duplication in Assignment editor. You may find example in FPGA Wiki page https://community.intel.com/t5/FPGA-Wiki/Register-Duplication-for-Timing-Closure/ta-p/735917 and document https://www.intel.com/content/dam/altera-www/global/en_US/uploads/a/aa/Register_Duplication_for_Timing_Closure.pdf

Thanks

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY