Timing Constraints with PLL clock muxes

[SK_VA]

I feed the output of pll to internal fpga logic that drives an output pin.

How to constrain the output with respect to the clock input of pll?

I am able to constrain w.r.t the output of pll

[KhaiChein_Y_Intel]

Is the output pin a data pin or clock output pin? May I know what kind of constraints you are referring to?

[sstrell]

If you are driving out a clock, you'll need a generated clock constraint targeted to that output port. The source of the generated clock will be the output pin of the PLL.

[SK_VA]

Hi,

I want to set output_delay and skew constraints on some output data pins w.r.t the referred clock.

I have 4 input clocks fed to 4 pins of FPGA. They are divided to 2 groups each with 2 clocks fed to 2 pll clock muxes. The out of these pll muxes are fed to one more mux. The final output of this mux is fed to the logic.

Now I am able to constrain w.r.t the output of pll clock muxes.

But I want to constrain my output data pins w.r.t to 4 input clocks that comes to FPGA.

Please refer the figure.I want to constrain w.r.t Cb1_clk1,Cb1_clk2,Cb2_clk1 and Cb2_clk2

[KhaiChein_Y_Intel]

You may constrain

create_generated_clock -name output_clock -source [get_ports  Cb1_clk1] [get_ports clk_out]

[SK_VA]

I tried this but it shows a warning that no such path exists.

[KhaiChein_Y_Intel]

Do you have output port for clock output?

[SK_VA]

I have ports for Cb1_clk,Cb2_clk and out_clk.

I think because of the PLL I am not able to constrain with respect to input clocks.