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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Timing analysis after analysis&synthesis step in Quartus 14.

BISIK
Beginner
883 Views

I want to find maximum frequency(or slack time) of an arithmetic operation in Quartus14. But Timequest analyzer, give a Run Fitter before Timequest error, when creating nets. Is there a way without complete place&route, doing timing analysis?

 

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sstrell
Honored Contributor III
127 Views

You can create a post-map timing netlist (you have to choose it manually from the Netlist menu in the timing analyzer) and perform an analysis on that, but it won't represent final timing in the design.

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3 Replies
GuaBin_N_Intel
Employee
127 Views
I presume NO for your question. To do any timing analysis, user must pass through synthesis and fitter. Without creation of netlist that targeting to a specific device, you won't get the Fmax result.
sstrell
Honored Contributor III
128 Views

You can create a post-map timing netlist (you have to choose it manually from the Netlist menu in the timing analyzer) and perform an analysis on that, but it won't represent final timing in the design.

BISIK
Beginner
127 Views

Thanks @sstrell​ , I know, there is an option in Vivado. After "synthesis", it's possible to see timing, results change after implementation bevause of routing factors.

But I wasn't sure in Quartus.

d.png

Then, as you say, I select post-timing from netlist menu. Netlist loaded in TimeQuest.

Thanks.

 

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