Timing constraints for output ports

[Altera_Forum]

Hi everyone, 

I've been puzzled by how to setup a timing constraints for a while now. Current design I am working on is not complicated (as a matter of fact, you may say it's very simple). It's running at very low speed (4.096MHz). So maybe timing constraints are not even necessary. However, as a beginner in FPGA design, I would like to do things the proper way. So I am posting here to ask the experts in the FPGA world how to constrain the timing for several IO ports. I've tried to read several documents and got more and more confused about what should I do. Anyway, I have attached a .pdf file to this post to describe my overall hardware and the FPGA functionality in block diagram. Also, in the .pdf file, I illustrated the idea input/output and some basic function waveforms. I've been trying to constrain the ports in this design and have the following constrains setup. So please comments on if I am doing the right thing or not. If not, please explain the correct approach.   .....  create_clock -name P2_Clk -period 30.518 [get_ports {P2}] # This is the 32.768MHz clock from the external CDR derive_pll_clocks derive_clock_uncertainty   set_clock_groups -asynchronous -group {} \ # some other clock group  -group {} \ # some other clock group  -group {P2_Clk   inst5|altpll_component|auto_generated|pll1|clk[0]} # IO constrains create_clock -name P2_Clk_ext -period 30.518 # As suggested by Ryan, created virtual clock for input set_input_delay -clock P2_Clk_ext -max 0.0 [get_ports {P1}] # Need to determine the max and min for the data input on this port  set_input_delay -clock P2_Clk_ext -min 0.0 [get_ports {P1}]  create_clock -name P4_ext -period 488.281 # This is basically the 2.048MHz sampling clock provided by FPGA to the HDB3 encoder set_output_delay -clock P4_ext -max -0 [get_ports P5] # The HDB3 encoder has a setup/hold time min requirment of 40 ns from the falling edge (chip is sampling on the falling edge) set_output_delay -clock P4_ext -min 0 [get_ports P5] ....  When I compile the design, Quartus is complaining that some path failed. Please see the attached word file. Looking at the waveform, I don't think I've constrains the output properly for Quartus to understand my design.   Any help is deeply welcomed!    Thanks

[Altera_Forum]

Some extra warming message from Quartus II which I don't quite understand 

Warning (332009): The launch and latch times for the relationship between source clock: inst5|altpll_component|auto_generated|pll1|clk[0] and destination clock: P4_ext are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.  Also, while I was trying to read relevent information online. I found something called "source-sychronize interfaces". In particular, Altera's website has a page on "Constraining a Center-Aligned Source-Synchronous Output", is that something that I am facing here for my P4 and P5? On the other hand, Altera AN433 suggested that for Single Data Rate source-synchronize interface, all I have to do is: set_output_delay -clock [get_clocks output_clk] -max 2 [get_ports data_out] set_output_delay -clock [get_clocks output_clk] -min -1[get_ports data_out] -add_delay 

[Altera_Forum]

Since the FPGA provides the clock to the HDB3 encoder, it's best to start by creating a clock on the FPGA's clock output pin. 

I assume P4 is the output of inst5|altpll_component|auto_generated|pll1|clk[0] create_clock -source inst5|altpll_component|auto_generated|pll1|clk[0] -name P4_clock [get_ports P4]  You can then specify your output delay constrains in regard to this P4_clock.  If your external device is sampling on the falling edge, then you should use -clock_fall P4_clock, instead of -clock P4_clock. If your device has a 40 ns tSu and a 40 ns Th, then you should specify that in the delays.  set_output_delay -clock_fall P4_clock -max 40 [get_ports P5] set_output_delay -clock_fall P4_clock -min -40 [get_ports P5]

[Altera_Forum]

PS: You don't need it now, but when you created the P4_ext clock, you probably gave it the wrong period. 

 You have a 30.518 ns P2 clock, which you then derive with a PLL to obtain P4.  I assume you get P4 by dividing P1 by 16. This means P4 will have a period of 30.518 * 16 => 488.288 ns (which is actually 2.04797169 MHz). Instead, you said P4_ext has a period of 488.281. This is a tiny difference, but it might cause problems with the tools.

[Altera_Forum]

P4 is actually drived from the output of the PLL. The FSM is running on the output clock of the PLL at 4.096MHz. The FSM drives P4 at 2.048 MHz. This relationship is useful to decoding CMI because it helps to sample the data stream twice during one bit interval. Therefore I have the launch clock running at 4.096MHz (because data is launched from the FSM). The latch clock is running at half the rate (2.048MHz). So how should I treat this 2.048MHz clock on P4 port? I believe it's a virtual clock as it doesn't interact with anything else inside the FPGA, but I am not sure how to constrain it? 

--- Quote Start ---  Since the FPGA provides the clock to the HDB3 encoder, it's best to start by creating a clock on the FPGA's clock output pin.I assume P4 is the output of inst5|altpll_component|auto_generated|pll1|clk[0]create_clock -source inst5|altpll_component|auto_generated|pll1|clk[0] -name P4_clock [get_ports P4]You can then specify your output delay constrains in regard to this P4_clock. If your external device is sampling on the falling edge, then you should use -clock_fall P4_clock, instead of -clock P4_clock.If your device has a 40 ns tSu and a 40 ns Th, then you should specify that in the delays.set_output_delay -clock_fall P4_clock -max 40 [get_ports P5]set_output_delay -clock_fall P4_clock -min -40 [get_ports P5]  --- Quote End ---  

[Altera_Forum]

Why I don't need P4_ext now? The virtual clock is mentioned everywheret in IO constrain. P4 is not directly drives by PLL. PLL divides the incoming clock (@32.768MHz) by 8 to get 4.096MH and the FSM runs on this 4.096MHz to generate 2.048MHZ. The reason why there's this small difference is because the truncation of the compiler. 

--- Quote Start ---  PS: You don't need it now, but when you created the P4_ext clock, you probably gave it the wrong period.You have a 30.518 ns P2 clock, which you then derive with a PLL to obtain P4. I assume you get P4 by dividing P1 by 16. This means P4 will have a period of 30.518 * 16 => 488.288 ns (which is actually 2.04797169 MHz).Instead, you said P4_ext has a period of 488.281. This is a tiny difference, but it might cause problems with the tools.  --- Quote End ---  

[Altera_Forum]

You apply the same concept: you create a derived clock at the output pin. 

However, you need 2 steps. First, create the 2.048 MHz clock at the output of the FSM create_generated_clock -source $pllClock -divide_by 2 -name "clk_2048" [get_registers fsm_clock_output]  Then, you create the P4_clock output from that create_generated_clock -source clk_2048 -name "P4_clock" [get_ports P4]   Virtual clocks are clocks which do not exist inside the FPGA. This clock exists, as it's generated inside the FPGA, even if does not drive any logic inside the FPGA. And in this case, it better represents your system than P4_ext. The "P4_ext" virtual clock you described has zero delay, in regard to the P2_clk. While the "P4_clock" does include all the delays inside the FPGA, from the P2_Clk pin to the PLL to the FSM to the P4 output pin.

[Altera_Forum]

Thanks rbugalho for replying. After creating P4_clk at the output pin, the rest still the same with regard to the set_output_delay min/max command? My guess is yes, but I could be wrong.Anyway, I'll try your suggestion on Monday. Have a nice weekend guys 

--- Quote Start ---  You apply the same concept: you create a derived clock at the output pin.However, you need 2 steps.First, create the 2.048 MHz clock at the output of the FSMcreate_generated_clock -source $pllClock -divide_by 2 -name "clk_2048" [get_registers fsm_clock_output]Then, you create the P4_clock output from thatcreate_generated_clock -source clk_2048 -name "P4_clock" [get_ports P4]Virtual clocks are clocks which do not exist inside the FPGA.This clock exists, as it's generated inside the FPGA, even if does not drive any logic inside the FPGA.And in this case, it better represents your system than P4_ext.The "P4_ext" virtual clock you described has zero delay, in regard to the P2_clk.While the "P4_clock" does include all the delays inside the FPGA, from the P2_Clk pin to the PLL to the FSM to the P4 output pin.  --- Quote End ---