VHDL code P2, Is anybody who can help me ?

[Altera_Forum]

Hi guys, 

I have some code for this "project" (photo). I have no idea hot to pair this. Can You help me with port map and signals ? This code is correct ? library IEEE; use IEEE.STD_LOGIC_1164.ALL;   entity projekt is port(Up,Down, : in std_logic; A0, A1, A2, A3: out std_logic); end projekt;   architecture projekt of projekt is begin  s1 <= up  s2 <=                         entity component is port (T: in std_logic Clock: in std_logic Out: out std_logic); signal tmp: std_logic; end component;       Architecture Behavioral of component is begin process (Clock) begin if Clock'event and Clock='1' then   if T='0' then tmp <= tmp; elsif T='1' then tmp <= not (tmp); end if; end if; end process; Out <= tmp; end przerzutnik;         begin T_FF: T1 port map(T T_FF: T2 port map T_FF: T3 port map T_FF: T4 port map

[Altera_Forum]

You appear to be missing all the port maps, plus I assume a copy paste error as the code is a little odd (there is a begin after the end) 

 Please re-post correct code and state what problems you're having

[Altera_Forum]

--- Quote Start ---  You appear to be missing all the port maps, plus I assume a copy paste error as the code is a little odd (there is a begin after the end)  Please re-post correct code and state what problems you're having  --- Quote End ---    I replicated only code for T flip-flop. Succession is not important bcs i know hot to sort this code. I don't know how to attribute signals and where they must be. Any suggestions?

[Altera_Forum]

What do you mean by "attribute signal"? 

The code is full of syntax errors and incomplete. So without a reasonable code example, and a specific problem, it is hard to understand what you want....

[Altera_Forum]

--- Quote Start ---  What do you mean by "attribute signal"? The code is full of syntax errors and incomplete. So without a reasonable code example, and a specific problem, it is hard to understand what you want....  --- Quote End ---    My teacher said : Later, you declare a component for the main unit, signals to connections, components and porting mapping ( with no logic describing how works flip flop) I know its uncomplete but want to know how it works, what is it ? And maybe i wll find code in the internet,I need it now rly, I don't asking for much, only to help with that.

[Altera_Forum]

The template is something like 

<libraries> entity name_of_module is <generic and port lists> end entity; architecture name_of_architecture of name_of_entity is <all aliases, signals components and constants> begin <processes, signal assignments, port maps etc> end architecture;  a generic/port map looks like   label : name_of_component generic map( some_gen => 0 ) port map ( clk => higher_level_clock );

[Altera_Forum]

--- Quote Start ---  The template is something like  <libraries> entity name_of_module is <generic and port lists> end entity; architecture name_of_architecture of name_of_entity is <all aliases, signals components and constants> begin <processes, signal assignments, port maps etc> end architecture;  a generic/port map looks like   label : name_of_component generic map( some_gen => 0 ) port map ( clk => higher_level_clock );   --- Quote End ---    Finally good reply:) Thank You o much !