VHDL code for simple calculation: b = 68 - (a/25)

[Altera_Forum]

I want to do a simple calculation in FPGA: 

b = 68 - (a/25)  Anyone help me how can I write VHDL code for this calculation? I try write this code but it fails. Can anybody correct this code?   signal a: std_logic_vector(10 downto 0); signal b: std_logic_vector(10 downto 0);   process(a)  variable tmp1: unsigned(10 downto 0);  variable tmp2: unsigned(10 downto 0); begin  tmp1 := unsigned(a)/25;  tmp2 := 68 - tmp1;   b<= std_logic_Vector(tmp2); end process;

[Altera_Forum]

I recommend to use package numeric_std from the IEEE library to ease the description of arithmetic calculations. In order to do, use the following clauses: 

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  The source code then becomes:  signal a: unsigned(10 downto 0); signal b: unsigned(10 downto 0);  process(a) variable tmp1: unsigned(10 downto 0); variable tmp2: unsigned(10 downto 0); begin  tmp1 := a / 25;  tmp2 := 68 - tmp1;   b <= tmp2; end process;  One last point: the results of 68-tmp1 may be negative (for example when a=2047). This may be a problem since tmp2 is declared as an unsigned...  --jmv

[Altera_Forum]

I am afraid that the division might not be that easy for synthesis. You should have a look at the MEGA WIZ divider.

[Altera_Forum]

The beauty of Quartus II integrated synthesis is that it is actually capable of inferring an lpm_divide megafunction from the VHDL "/" operator.  

 --jmv

[Altera_Forum]

The question is, how quick it is. I found more than 10clocks delay to be setup in the wizzard for are divider in order to be able to calc with the necessary width (48bits in my app) and meet the reqs of the given clock freq. 

 I wonder what freq could be achieved with a divider of here 10bits in one clock cycle ?

[Altera_Forum]

Thank you jmv! 

Quartus understand the division "\". It takes about some clocks to do this calculation.