Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16593 Discussions

Warning(16226): One or more registers failed to be packed into a DSP bank ...

SShiv1
Beginner
1,383 Views

could you please send me the updated template as early as possible.

0 Kudos
2 Replies
Nooraini_Y_Intel
Employee
465 Views

Hi,

 

Is this thread is the same issue/request as in the following thread link? If this is the not same thread, please of provide details/steps on this issue(error) replication.

https://forums.intel.com/s/question/0D50P0000476TgTSAU/adder-is-not-packed-into-a-dsp-block-in-1st280ey2f55e2lgs1-fpga?t=1544024594670

 

Regards,

Nooraini

0 Kudos
CheePin_C_Intel
Employee
465 Views

​Hi,

 

I believe this register packing issue is due to the same reason as the forum:

 

https://forums.intel.com/s/question/0D50P0000476TgTSAU/adder-is-not-packed-into-a-dsp-block-in-1st280ey2f55e2lgs1-fpga?t=1544071243898

 

You may refer to the above forum ie to use Native DSP IP or the S10 DSP template to pack the register into DSP bank.

 

Thank you very much.

 

Chee Pin

0 Kudos
Reply