Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16611 Discussions

Warning during simulation using modelsim 10.4b

Altera_Forum
Honored Contributor II
1,564 Views

Hi all, 

While running a design verification generated via qsys testbench, I'm continuously monitoring sink bfm for any new data/packet. During this, i get this warning. 

 

*** warning: vl_init_value, unknown td kind:0 

 

I get it frequently, but not always. I'm not getting whether it is warning related to design(Quartus Design Files) or Modelsim. 

It doesn't affect the verification but gets replicated in transcript multiple times that it gets difficult to analyze the printed output data. 

 

Any leads will be helpful. Thanks in advance!
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
606 Views

*** warning: vl_init_value, unknown td kind:0 

 

I got this exact error. I had just put in a line of code -- localparam test = 30; and I got dozens of these messages. I put that line of code at the top of the module and they all went away!
0 Kudos
Altera_Forum
Honored Contributor II
606 Views

I also saw this warning when I compiled a file by itself. I reran my compile script and it all worked again. I suggest playing with the compile order.

0 Kudos
Reply