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Novice
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Working on exercise #2 and found this error at step 5: "Error (12006): Node instance "lpm_mult_inst" instantiates undefined entity "lpm_mult".

Would you mind show me what causes this error?

Note: I am using Quartus Prime Lite 16.1 to do the exercise that suggests for Quartus® Prime Standard Edition software version 15.1

 

Below is the piece of code that the error points to.

-- megafunction wizard: %LPM_MULT%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: lpm_mult 

 

-- ============================================================

-- File Name: mult.vhd

-- Megafunction Name(s):

-- lpm_mult

--

-- Simulation Library Files(s):

-- lpm

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 16.1.0 Build 196 10/24/2016 SJ Lite Edition

-- ************************************************************

 

 

--Copyright (C) 2016 Intel Corporation. All rights reserved.

--Your use of Intel Corporation's design tools, logic functions 

--and other software and tools, and its AMPP partner logic 

--functions, and any output files from any of the foregoing 

--(including device programming or simulation files), and any 

--associated documentation or information are expressly subject 

--to the terms and conditions of the Intel Program License 

--Subscription Agreement, the Intel Quartus Prime License Agreement,

--the Intel MegaCore Function License Agreement, or other 

--applicable license agreement, including, without limitation, 

--that your use is for the sole purpose of programming logic 

--devices manufactured by Intel and sold by Intel or its 

--authorized distributors. Please refer to the applicable 

--agreement for further details.

 

 

LIBRARY ieee;

USE ieee.std_logic_1164.all;

 

LIBRARY lpm;

USE lpm.all;

 

ENTITY mult IS

PORT

(

clock : IN STD_LOGIC ;

dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

);

END mult;

 

ARCHITECTURE SYN OF mult IS

 

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);

 

COMPONENT lpm_mult

GENERIC (

lpm_hint : STRING;

lpm_pipeline : NATURAL;

lpm_representation : STRING;

lpm_type : STRING;

lpm_widtha : NATURAL;

lpm_widthb : NATURAL;

lpm_widthp : NATURAL

);

PORT (

clock : IN STD_LOGIC ;

dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

);

END COMPONENT;

 

BEGIN

result  <= sub_wire0(15 DOWNTO 0);

 

lpm_mult_component : lpm_mult

GENERIC MAP (

lpm_hint => "MAXIMIZE_SPEED=5",

lpm_pipeline => 2,

lpm_representation => "UNSIGNED",

lpm_type => "LPM_MULT",

lpm_widtha => 8,

lpm_widthb => 8,

lpm_widthp => 16

)

PORT MAP (

clock => clock,

dataa => dataa,

datab => datab,

result => sub_wire0

);

 

END SYN;

 

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8 Replies
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Employee
11 Views

Hi TRI, Could you please provide a bit more details? 1. which exercise #2 are you working ? please provide link. 2. Device used. Check the entity & component declaration of "lpm_mult". Regards, Vikas
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Highlighted
Novice
11 Views

Hi Vicky, First, thanks for helping me out. Attached is the Exercise manual found in Quartus Full Day Lab Manual. Regards, Tri Dang Tel: 858-676-7418
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Highlighted
Employee
11 Views

Hi Tri Dang, Have you resolved the issue? Regards, Vikas
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Highlighted
Novice
11 Views

Pipemult Screenshot.pngHi Victor,

Yes, I did try your suggestions and the issue is still persisted.

Attached is the project file. If you can look at it and tell me what was missing/wrong I'd appreciated.

BTW, below is the message that is produced from Processing->Start->Start Analysis & Elaboration

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Highlighted
Employee
11 Views

Hi Tri Dang,

Thanks for the all the details.

Actually I tried to replicate the issue but I could able to do full compilation,please find the attachment.

1. Can you upgrade the IPs with "Launch the IP upgrade tool" highlighted in yellow colour.

2. Check the Quartus Root Directory,

System-> Advanced System Settings ->Environmental Variables..-> ( to the 16.1 lite)

please let me know if this has helped to resolve the issue.

LPM_MULT.JPGEnvironment_variable.png

Regards,

Vikas

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Highlighted
Retired Employee
11 Views

It looks like you named the IP "multop" looking at your screenshot which I don't think is the correct name. If the name of the IP and its file doesn't match the top-level as described in the instructions for the lab, you'll get an error.

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Highlighted
Novice
11 Views

Hi Vikas,

I cannot open "Advanced System Settings" to check due to my laptop is locked by IT. If you are able to compile this project/exercise with you Quartus 16.1.0 Lite I think I will try it later with different computer.

I don't know if security has anything to do with the error that I had.

I will try this exercise with my home laptop this weekend.

Thanks for your help.

 

TDang

 

Highlighted
Employee
11 Views

Hi TDang, You can also check on current system by recreating the(IPs) & recompiling the design. Regards, Vikas
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