Writing Fast State Machines using SystemVerilog

[Altera_Forum]

Hello, I came across this article that commented on using State Machines with One-Hot encoding.  

 http://www.verilogpro.com/systemverilog-one-hot-state-machine/  The article state,   "According to Cliff Cummings’ 2003 paper, this coding style yields poor performance because the Design Compiler infers a full 4-bit comparison against the state vector, in effect defeating the speed advantage of a one-hot state machine."  Can anyone recommend the best method to achieve speed?  Thanks, Joe

[Altera_Forum]

I always encode states 0 to 2^N-1 for an N-state state machine and let the synthesis tool decide how to build it. Quartus almost always encodes state machines one-hot anyway.

[Altera_Forum]

As the end of that article states, that paper is from 2003. Synthesis tools are much smarter now. One-hot is still most efficient which is why Quartus defaults to it.

[Altera_Forum]

For state machines with 3 or more states, it infers 1 hot by default. But you can force it to use counter or grey (or others) code using attributes or synthesis directives: 

 http://quartushelp.altera.com/15.0/mergedprojects/hdl/vlog/vlog_file_dir_syn_encoding.htm