Wrong resource usage for MAX V design

[Zak]

Hello,

I'm performing a feasibility study for a custom project and I need to estimate the resource usage of a test design on a MAX V device: 5M160ZE64I5.

I've never used MAX V, I've experience with Cyclone V devices only.

I don't understand why the fitter report doesn't change when I add, remove or edit my VHDL code. I also added a QSYS design with SPI slave and few Avalon MM peripherals but the fitter report doesn't change and shows always a success. For example, I always get 44/160 (28%) logic elements, even If I add a signal generated by a process with a 64 bit counter...

Also, in the "Resource Utilization by Entity" report tab I see ONLY the top level entity. With Cyclone V and other designs I could see all the entities with the associated resource utilization.

Since the design is very simple, I wrote an SDC file with a clock definition and false paths for the I/Os.

The pins are correctly assigned in the Pin Planner.

Can someone tell me what can I check to solve this issue? Am I missing something?
Thank you!

[Zak]

I forgot to add that I'm currently using Quartus 18.1.0 build 625.

[sstrell]

If you're only seeing the top-level entity in the report, perhaps the rest of the files have not been added to the project.  Go to Project->Add/Remove Files and make sure all the files that make up the project are added.

[KennyTan_Altera · Accepted solution]

Another possible situation that your design had been optimized away. You can look for the analysis report to get those information

[Zak]

Yes, that's just it! Since it is a test design some entity outputs weren't connected...

The weird thing is also a PIO and an SPI Slave to Avalon Master IP cores are optimized away with no reason. Both IPs have I/Os connected to I/O pads and are linked together with an Avalon bus.

Anyway, thanks to led me towards an explanation of this phenomenon.