Re: Yet another PUF issue.

Altera_Forum · ‎10-27-2008

Hi all. I asked some PUF related questions on these boards before, and I am still looking for a good way to implement a PUF on the Altera FPGAs using Quartus II.

So far I've tried:

Race based multiplexer PUFs

Race based carry-chain delay PUF

Race based buffer delay PUF

Ring oscillator based PUF

I'm now trying a new type of PUF called a Butterfly PUF (BPUF). An explanation can be found here:

Fig.3: http://www.cosic.esat.kuleuven.be/publications/article-1154.pdf

My problem is that when I try implementing this PUF, Quartus seems to optimize away the latches. I've solved optimization in the past by including LCELLs or using the "synthesis keep" attribute. How can I make sure the latches are kept? The reason I believe they are removed is that Quartus can't locate them in the floorplan viewer.

Here's my code for the latch:

module Clatch(
	D,
	CLK,
	PRE,
	CLR,
	Q
);
input D;
input CLK;
input PRE;
input CLR;
output Q;
reg latch1 /* synthesis keep*/;
assign	Q = latch1;
always@(posedge CLK or negedge PRE or negedge CLR)
begin
if (!PRE)
	begin
	latch1 <= 1;
	end
else
if (!CLR)
	begin
	latch1 <= 0;
	end
else
	begin
	latch1 <= D;
	end
end
endmodule

Altera_Forum · ‎10-27-2008

--- Quote Start ---

Hi all. I asked some PUF related questions on these boards before, and I am still looking for a good way to implement a PUF on the Altera FPGAs using Quartus II.

So far I've tried:

Race based multiplexer PUFs

Race based carry-chain delay PUF

Race based buffer delay PUF

Ring oscillator based PUF

I'm now trying a new type of PUF called a Butterfly PUF (BPUF). An explanation can be found here:

Fig.3: http://www.cosic.esat.kuleuven.be/publications/article-1154.pdf

My problem is that when I try implementing this PUF, Quartus seems to optimize away the latches. I've solved optimization in the past by including LCELLs or using the "synthesis keep" attribute. How can I make sure the latches are kept? The reason I believe they are removed is that Quartus can't locate them in the floorplan viewer.

Here's my code for the latch:

module Clatch(
	D,
	CLK,
	PRE,
	CLR,
	Q
);
input D;
input CLK;
input PRE;
input CLR;
output Q;
reg latch1 /* synthesis keep*/;
assign	Q = latch1;
always@(posedge CLK or negedge PRE or negedge CLR)
begin
if (!PRE)
	begin
	latch1 <= 1;
	end
else
if (!CLR)
	begin
	latch1 <= 0;
	end
else
	begin
	latch1 <= D;
	end
end
endmodule

--- Quote End ---

Hi,

I setup a project with your code. What is wrong with the result ?

Altera_Forum · ‎10-27-2008

Are you finding the latch in the floorplan?

Altera_Forum · ‎10-27-2008

--- Quote Start ---

Are you finding the latch in the floorplan?

--- Quote End ---

Yes,

open the technology view, select the latch and choose Locate in Chip planner.

Altera_Forum · ‎10-27-2008

Oh, I see it now. When I directly use the Chip Planner, I get a "Cannot find requested location" error.

So here is another question: when I connect two DFFs in the manner that is described in the paper I get this verilog code:

module BPUFelement(
	stableZero,
	clk,
	excite,
	out
);
input	stableZero;
input	clk;
input	excite;
output	out;
reg	DFF_inst1;
reg	DFF_inst;
assign	out = DFF_inst;
always@(posedge clk or negedge excite or negedge stableZero)
begin
if (!excite)
	begin
	DFF_inst <= 0;
	end
else
if (!stableZero)
	begin
	DFF_inst <= 1;
	end
else
	begin
	DFF_inst <= DFF_inst1;
	end
end
always@(posedge clk or negedge stableZero or negedge excite)
begin
if (!stableZero)
	begin
	DFF_inst1 <= 0;
	end
else
if (!excite)
	begin
	DFF_inst1 <= 1;
	end
else
	begin
	DFF_inst1 <= DFF_inst;
	end
end
endmodule

Won't this always give a result of 0? The paper says to set stableZero to 0, excite to 1, then drop to 0, and clk to 1.

Altera_Forum · ‎10-28-2008

The drawing in the paper, particularly the designatator clk is possibly misleading. With a DFF, as in your code, the circuit is completely stable. The unstable operation is achieved with a latch respectively a combinational loop. Most FPGA families don't have hardware latches of the shown kind, thus the circuit has to be formed by two logic cells.

If I understand right, the latch signal clk is always enabled and the clr signal is unused.

Altera_Forum · ‎10-28-2008

--- Quote Start ---

Oh, I see it now. When I directly use the Chip Planner, I get a "Cannot find requested location" error.

So here is another question: when I connect two DFFs in the manner that is described in the paper I get this verilog code:

module BPUFelement(
	stableZero,
	clk,
	excite,
	out
);
input	stableZero;
input	clk;
input	excite;
output	out;
reg	DFF_inst1;
reg	DFF_inst;
assign	out = DFF_inst;
always@(posedge clk or negedge excite or negedge stableZero)
begin
if (!excite)
	begin
	DFF_inst <= 0;
	end
else
if (!stableZero)
	begin
	DFF_inst <= 1;
	end
else
	begin
	DFF_inst <= DFF_inst1;
	end
end
always@(posedge clk or negedge stableZero or negedge excite)
begin
if (!stableZero)
	begin
	DFF_inst1 <= 0;
	end
else
if (!excite)
	begin
	DFF_inst1 <= 1;
	end
else
	begin
	DFF_inst1 <= DFF_inst;
	end
end
endmodule

Won't this always give a result of 0? The paper says to set stableZero to 0, excite to 1, then drop to 0, and clk to 1.

--- Quote End ---

I tried to model the required behaviour. Look into the Quartus project, maybe it would help you further.

Altera_Forum · ‎10-28-2008

I appreciate you taking the time to try to model the behavior pletz. I'm pasting the code here, so we can discuss easier.

module BPUFelement(
	excite,
	clk,
	out
);
input	excite;
input   clk;
output	out;
wire net1, net2;
 preset_latch latch_i1 (.clk(clk),.D(net2),.pre(excite),.Q(net1));
 reset_latch latch_i2 (.clk(clk),.D(net1),.clr(excite),.Q(net2));
 
 assign out = net2;
endmodule
module preset_latch (pre,D,Q,clk);
input pre,D,clk;
output Q;
reg reg_int;
always@(pre or D or clk) begin 
 if (clk)
	begin
	 if(pre)
	  reg_int <= 1;
	end  
 else reg_int <= D ;
	
end
assign Q = reg_int;
endmodule
module reset_latch (clk,D,Q,clr);
input clr,D,clk;
output Q;
reg reg_int;
always@(clr or D or clk) begin 
 if (clk)
	begin
	 if(clr)
	  reg_int <= 0;
	end  
 else reg_int <= D ;
	
end
assign Q = reg_int;
endmodule

According to the description in the paper, it seems to me that the circuit follows these rules:

Excite = 1, then drops to 0

CLK = 1, always

if CLK = 1, then Q = D

if PRE = 1, then Q = 1

if CLR = 1, then Q = 0

seems from the code above that only if CLK = 0, then Q = D? Wouldn't it be more accurate to say:


always@(clr or D or clk) begin 
if (clk)
  begin
	if(clr) reg_int <= 0;
	else reg_int <= D ;
  end
end

If I make that change to the preset_latch and reset_latch modules, and run a simulation, I get the following result:

http://img262.imageshack.us/img262/9418/simres1qu3.th.jpg (http://img262.imageshack.us/my.php?image=simres1qu3.jpg)http://img262.imageshack.us/images/thpix.gif (http://g.imageshack.us/thpix.php)

and zoomed in:

http://img262.imageshack.us/img262/337/simres2wc0.th.jpg (http://img262.imageshack.us/my.php?image=simres2wc0.jpg)http://img262.imageshack.us/images/thpix.gif (http://g.imageshack.us/thpix.php)

it seems that the circuit is stabilizing on a particular value, which here happens to be 1. I haven't tried this on a real board yet, but I will later today.

Altera_Forum · ‎10-29-2008

So I tried implementing this on an Altera DE2 board. I used the 7seg display to output 32 bits. I used toggle switches to control the always-high "CLK" signal, and the "excite" signal.

The results across 3 different boards were different, but not 100% different. About half the hex digits were the identical between the boards. Between different inputs, the results were also different, but again, not 100%.

I'm not sure if this can be remedied.

I have a concern about the compilation and how the amount of logic cells used on each of the 32 sections (BPUFslice) of the BPUF seem to be different. As shown in the screenshot.

Is this normal? Would the results improve if an equal amount of cells were used to create each section?

Also, can I manually set where the sections are placed on the chip?

I included the project if you guys wanna take a look.

Thanks! :)

http://img128.imageshack.us/img128/5823/lcsay6.th.jpg (http://img128.imageshack.us/my.php?image=lcsay6.jpg)http://img128.imageshack.us/images/thpix.gif (http://g.imageshack.us/thpix.php)

Altera_Forum · ‎10-29-2008

There are several module sources missing from the project.

As you can see from the technology map view, the basic bpufslice is made up as a combinational loop through six logic cells, making it difficult to force a more symmetric place and route of the design manually. I would try with a slice that uses less logic cells.

I already didn't understand the purpose of the one signal, that requires some of the extra logic cells.

Generally, the result seems to confirm my assumption from the previous PUF discussion:

--- Quote Start ---

As one point, it seems questionable if the accidental delay skew, that is utilized by this technique, has a considerable amount compared to systematic and reproducable routing delays.

--- Quote End ---

Altera_Forum · ‎10-29-2008

I removed the "one" input, and changed it to a wire in the design. This produced a compiled circuit with 0 logic cells... Fewer Logic Cells indeed. :)

Sorry about the missing files. I re-uploaded the project.

Altera_Forum · ‎10-29-2008

Actually, I was able to make a design where all BPUFslice instance uses 17 logic cells, by turning the top view to verilog and using the /* synthesis keep */ attribute on the C wire, which was missing from certain instances before. The results were not great however... :(

3/4 DE2 boards gave the same value.