I have a VHDL blackbox file my_file_bb.vhd in which I declare all the input and output ports.
When I instantiate it from another program ... entity TEST: my_file port map.... Quartus keeps complaining that object my_file is used but not declared. I thought the blackbox file already takes care of all the declarations. Do I need to do anything else to use the blackbox file?
The issue here is you've used the VHDL black box module without declaring it. Before you use the BB module in your VHDL Architecture block via a Port Map, you have to declare the BB module as a Component. All you need to do is to add a component declaration for the black box module under the Architecture block and then use it in the Port Map.
Architecture RTL of XXX Is
Component my_file Is
Port Map ( );
It should resolve the issue. Else post back with your code and we'll help you resolve it.