can you find the small error for me,sir............ :(

[Altera_Forum]

this is the time to show in LCD. i cannot find the problem. i want to show hour for 01-12. but its also include 00. so after 12hr it become 00hr and then 01 hr. that is the wrong. can u find the error, sir. plz help me. that is very important for me ................. thank sir 

  ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;   entity counter_up is  Port ( clk : in STD_LOGIC;  SET : in STD_LOGIC;  BTN0 : in STD_LOGIC;  BTN1 : in STD_LOGIC;  BTN2 : in STD_LOGIC;  BTN3 : in STD_LOGIC;  BTN4 : in STD_LOGIC;  BTN5 : in STD_LOGIC;  reset : in STD_LOGIC;  AM : out STD_LOGIC;  hex0 : out STD_LOGIC_VECTOR (3 downto 0);  hex1 : out STD_LOGIC_VECTOR (3 downto 0);  hex2 : out STD_LOGIC_VECTOR (3 downto 0);  hex3 : out STD_LOGIC_VECTOR (3 downto 0);  hex4 : out STD_LOGIC_VECTOR (3 downto 0);  hex5 : out STD_LOGIC_VECTOR (3 downto 0)); end counter_up;   architecture Behavioral of counter_up is signal count0:std_logic_vector(3 downto 0):=(others=>'0'); signal count1:std_logic_vector(3 downto 0):=(others=>'0'); signal count2:std_logic_vector(3 downto 0):=(others=>'0'); signal count3:std_logic_vector(3 downto 0):=(others=>'0'); signal count4:std_logic_vector(3 downto 0):=x"1"; signal reg:std_logic:='0'; begin   process(clk,reset) begin  if reset='1' then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<=x"1";  elsif rising_edge(clk) then  if SET='1' then  if (count0=x"9" and BTN0='1') then  count0<=x"0";  elsif (BTN0='1') then  count0<=count0+1;  elsif (count1=x"5" and BTN1='1') then  count1<=x"0";  elsif (BTN1='1') then  count1<=count1+1;  elsif (count2=x"9" and BTN2='1') then  count2<=x"0";  elsif (BTN2='1') then  count2<=count2+1;  elsif (count3=x"5" and BTN3='1') then  count3<=x"0";  elsif (BTN3='1') then  count3<=count3+1;   elsif (count4=x"C" and BTN4='1') then  count4<=x"1";  elsif (BTN4='1') then  count4<=count4+1;   elsif(BTN5='1') then  reg<=not(reg);   end if;   else  if (count4=x"C" and count3=x"5" and count2=x"9" and count1=x"5" and count0=x"9") then  reg<=not(reg);  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<= x"1";   elsif (count3=x"5" and count2=x"9" and count1=x"5" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=(others=>'0');  count4<=count4 + 1;  elsif (count2=x"9" and count1=x"5" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=(others=>'0');  count3<=count3 + 1;   elsif (count1=x"5" and count0=x"9") then  count0<=(others=>'0');  count1<=(others=>'0');  count2<=count2 + 1;  elsif (count0=x"9") then  count0<=(others=>'0');  count1<=count1 + 1;  else  count0<=count0 + 1;  end if;   end if;      end if; end process;     AM <= reg; hex0<=count0; hex1<=count1; hex2<=count2; hex3<=count3; hex4<= count4 when (count4<x"A") else "00"&count4(2 downto 1) when count4=x"C" else "00"&count4(0);   hex5<= "0001" when (count4=x"A" or count4=x"B" or count4=x"C") else "0000"; end Behavioral;

[Altera_Forum]

The error is here: 

count4 when (count4<x"A") else "00"&count4(2 downto 1) when count4=x"c" else "00"&count4(0); The bold part is wrong and pointless.  count4 when (count4<x"A") else x"2" when count4=x"C" else  "000"&count4(0);

[Altera_Forum]

... probably the error is not this. I see now you described a different behavior

[Altera_Forum]

there is nothing change sir when i wrote as u said

[Altera_Forum]

can u tell me more detail? 

where is different behavior

[Altera_Forum]

Wow that is working sir. 

Thank you so much If u don't mind plz explain me how to change .pof file extension  I changed in the file convertor. But it's not work. It shows the error sms.