compiling a design that instantiate 4096 times the same module

[Altera_Forum]

Hi, 

I'm writing a vhdl top code that instantiates 4096 the same module (using vhdl generate statement).  The module consists in a RAM, plus an adder and some other logic ... and 4096 of them saturates the biggest stratix V that Altera have ... It takes about 6 hours compile time ...  I wonder if exist a standard compile and place route procedure to perform this kind of designs, like compiling the single module only one time and  then placing the block 4096 times ... I'm new to this kind of modular and repetitive designs so can someone explain me which is the usual way of proceeding ? Using logiblocks or partitions or something else could help ?  Thanks a lot franco

[Altera_Forum]

--- Quote Start ---  Hi, I'm writing a vhdl top code that instantiates 4096 the same module (using vhdl generate statement).  The module consists in a RAM, plus an adder and some other logic ... and 4096 of them saturates the biggest stratix V that Altera have ... It takes about 6 hours compile time ...  I wonder if exist a standard compile and place route procedure to perform this kind of designs, like compiling the single module only one time and  then placing the block 4096 times ... I'm new to this kind of modular and repetitive designs so can someone explain me which is the usual way of proceeding ? Using logiblocks or partitions or something else could help ?  Thanks a lot franco  --- Quote End ---    Your question is wrong. Does it fit or not the available resource. If not then why ask how to fit it.

[Altera_Forum]

Wow. 4096. Why so many? like you said, you can only fit it in the largest stratix V. So have you got $10k lying around?

[Altera_Forum]

Btw, using a generate loop is the only way to place it. Logic locks just lock down existing code. and partitions are just pre-compiled code. But you still need the code.

[Altera_Forum]

--- Quote Start ---  Btw, using a generate loop is the only way to place it. Logic locks just lock down existing code. and partitions are just pre-compiled code. But you still need the code.  --- Quote End ---    Yes it fits but to compile takes many hours, so I wonder if the force brute technique is the right one ... If it were a standard cell I would define and compile a cell then I would place it all the needed times getting a regular structure. In this case I have to compile the same module 4096 times ... Maybe I should use another compiler - synthetizer in top of quartus ? thanks franco

[Altera_Forum]

I don't know of any. 

It looks like a hard problem anyway. Unlike an ASIC, where you can create a block and then simply replicate it exactly, in an FPGA each "identical" block has to be fitted to the FPGA logic and interconnect resources, making each one slightly different.  6 hour compile time sounds about right for a full big FPGA.

[Altera_Forum]

yup, 6 hours about right. 

I currently have a 80% full Stratix 4 that takes 4 hours on an i7, or 17 hours if I run DSE with 12 parrallel compiles (and It never meets timing) on the 6 core Xeon server.  Welcome to full FPGA compilations.

[Altera_Forum]

In principle, LogicLock can be applied to multiple instances of a precompiled design entity, using floating location. 

 But I doubt that it's helpful in the present case.