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emulated lvds

Altera_Forum
Honored Contributor II
‎06-30-2008 10:08 AM
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what is the difference between emulated lvds and true lvds? 

 

from DE3 user manual 

"On bank 2 and 3, the I/O pins used in differential transmitter channels support emulated LVDS via a termination resistor" 

 

i understand that it involves setting the value of a termination resistor (in assignment editor) 

 

how does its performance compare with true lvds? can they be used simultaneously, with one channel being driven by true LVDS and 2nd channel by emulated lvds  

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Altera_Forum
Honored Contributor II
‎06-30-2008 06:24 PM
767 Views

Termination schemes are discussed in Stratix III manual figure 7–25. stratix iii lvds i/o standard termination. The emulated LVDS output technique require either one (LVDS_E_1R, up to 200 MBPS) or three (LVDS_E_3R) external resistors. Furthermore, the Stratix III pinout-files have a column showing possible emulated LVDS output assignment. 

 

Please notice that what Terasic designates banks at HSTC connectors hasn't to do with FPGA IO-Banks.
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