help!!

[Altera_Forum]

I'm creating a code now, which i need to increase the input A,B by 2 after each state.  

Example  @s0: A=00000001, B=00000010.  @s1: I want A= 00000011 and B= 00000100. How do i do it?   And i know there's something wrong with my code, highlighted in red. As i need help for this. Can someone help?  This is code.    library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.All;   -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;   -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;   entity Project3M2A is  Port ( A : in STD_LOGIC_VECTOR (7 downto 0);  B : in STD_LOGIC_VECTOR (7 downto 0);  W : out STD_LOGIC_VECTOR (7 downto 0);  X : out STD_LOGIC_VECTOR (7 downto 0);  Y : out STD_LOGIC_VECTOR (7 downto 0);  Z : out STD_LOGIC_VECTOR (7 downto 0);  LOAD : in STD_LOGIC;  RST : in STD_LOGIC;  CLK : in STD_LOGIC); end Project3M2A;   architecture Behavioral of Project3M2A is     type state_type is (S0,S1,S2);--,S3,S4,S5,S6,S7,S8,S9,S10); signal state, state_next: state_type; signal add1_op0,add1_op1,add2_op0,add2_op1: signed ( 16 downto 0); signal mult_op0,mult_op1: signed (16 downto 0); signal R1,R2,R3,R4,R5,R6: signed (7 downto 0 );--R3,R4,R5,R6: std_logic_Vector (7 downto 0 ); --signal R5,R6,R7,R8,R9,R10,R11,R12: std_logic_Vector (7 downto 0 ); signal R1_next,R2_next,R3_next,R4_next,R5_next,R6_next: signed( 7 downto 0);--,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next: std_logic Vector( 7 downto 0); signal prod: signed (33 downto 0); begin     P1: process(clk,rst) is  begin  if rst='0' then  state<=S0;  r1 <= (others => '0');  r2 <= (others => '0');  r3 <= (others => '0');  r4 <= (others => '0');  r5 <= (others => '0');  r6 <= (others => '0');  --r7 <= (others => '0');  --r8 <= (others => '0');  --r9 <= (others => '0');  --r10 <= (others => '0');  --r11 <= (others => '0');  --r12 <= (others => '0');  --r6 <= (others => '0');  --r7 <= (others => '0');  elsif(clk'event and clk='1') then   state <=state_next; -- next state update  r1<=r1_next;-- update next state at rising edge of clk  r2<=r2_next;  r3<=r3_next;  r4<=r4_next;  r5<=r5_next;  r6<=r6_next;  --r7<=r7_next;  --r8<=r8_next;  --r9<=r9_next;  --r10<=r10_next;  --r11<=r11_next;  --r12<=r12_next;  end if; end process P1; P2: process (load, state,r1,r2,r3,r4,r5,r6, A,B)  begin   r1_next<=r1;-- keep previous data if not updated  r2_next<=r2;  r3_next<=r3;  r4_next<=r4;  r5_next<=r5;  r6_next<=r6;  --r7_next<=r7;  --r8<=r8_next;  --r9<=r9_next;  --r10<=r10_next;  --r11<=r11_next;  --r12<=r12_next;  --complete<='0';  case state is  when S0 => if load ='1' then  r1_next<= signed (A(7 downto 0));  r2_next<= signed (B(7 downto 0));    state_next<=S1;  --complete<='1';  else  state_next<=S0;  end if;  when S1=>   r3_next<=signed (A(7 downto 1)& "0");  r4_next<=signed (B(7 downto 1)& "0");  state_next<= S2;  when S2=>   r5_next<=signed (A(7 downto 2)& "00");  r6_next<=signed (B(7 downto 2)& "00");  state_next<=S0;  end case;  end process p2;   end Behavioral;

[Altera_Forum]

The next signals all append 0 to the bottom of the word. Therefore not really doing a lot. 

 if you want to increment by 2, why not write:  r3_next <= signed(A) + 2;

[Altera_Forum]

--- Quote Start ---  The next signals all append 0 to the bottom of the word. Therefore not really doing a lot.  if you want to increment by 2, why not write:  r3_next <= signed(A) + 2;  --- Quote End ---         library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.All;   -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;   -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;   entity Project3M2A is  Port ( A : in STD_LOGIC_VECTOR (7 downto 0);  B : in STD_LOGIC_VECTOR (7 downto 0);  W : out STD_LOGIC_VECTOR (7 downto 0);  X : out STD_LOGIC_VECTOR (7 downto 0);  Y : out STD_LOGIC_VECTOR (7 downto 0);  Z : out STD_LOGIC_VECTOR (7 downto 0);  LOAD : in STD_LOGIC;  COMPLETE: out STD_LOGIC;  RST : in STD_LOGIC;  CLK : in STD_LOGIC); end Project3M2A;   architecture Behavioral of Project3M2A is     type state_type is (S0,S1,S2,S3,S4,S5,S6);--,S3,S4,S5,S6,S7,S8,S9,S10); signal state, state_next: state_type; signal add1_op0,add1_op1,add2_op0,add2_op1: signed ( 7 downto 0); signal mult1,mult2,mult3,mult4: signed (7 downto 0); signal R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12: signed (7 downto 0 );--R3,R4,R5,R6: std_logic_Vector (7 downto 0 ); signal R13,R14,R15,R16,R17,R18,R19,R20: signed (7 downto 0 ); -- Registers for doing X and + signal R1_next,R2_next,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next: signed( 7 downto 0);--,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next: std_logic Vector( 7 downto 0); signal R13_next,R14_next,R15_next: signed( 7 downto 0); signal prod1,prod2,prod3: signed (7 downto 0); begin     P1: process(clk,rst) is  begin  if rst='0' then  state<=S0;  r1 <= (others => '0');  r2 <= (others => '0');  r3 <= (others => '0');  r4 <= (others => '0');  r5 <= (others => '0');  r6 <= (others => '0');  r7 <= (others => '0');  r8 <= (others => '0');  r9 <= (others => '0');  r10 <= (others => '0');  r11 <= (others => '0');  r12 <= (others => '0');  r6 <= (others => '0');  r7 <= (others => '0');  elsif(clk'event and clk='1') then   state <=state_next; -- next state update  r1<=r1_next;-- update next state at rising edge of clk  r2<=r2_next;  r3<=r3_next;  r4<=r4_next;  r5<=r5_next;  r6<=r6_next;  r7<=r7_next;  r8<=r8_next;  r9<=r9_next;  r10<=r10_next;  r11<=r11_next;  r12<=r12_next;  r13<=r13_next;  r14<=r14_next;  end if; end process P1; P2: process (load, state,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14, A,B)  begin   r1_next<=r1;-- keep previous data if not updated  r2_next<=r2;  r3_next<=r3;  r4_next<=r4;  r5_next<=r5;  r6_next<=r6;  r7_next<=r7;  r8<=r8_next;  r9<=r9_next;  r10<=r10_next;  r11<=r11_next;  r12<=r12_next;  r13<=r13_next;  r14<=r14_next;  complete<='0';  case state is  when S0 => if load ='1' then  r1_next<= signed (A(7 downto 0));  r2_next<= signed (B(7 downto 0));  state_next<=S1;  complete<='1';  else  state_next<=S0;  end if;  when S1=> if load ='1' then  r3_next<=signed (A) +2;  r4_next<=signed (B) +2;  state_next<= S2;  --complete<='1';  else   state_next<=S1;  end if;  when S2=> if load ='1' then  r5_next<=signed (r3_next)+2;  r6_next<=signed (r4_next)+2;  state_next<=S3;  else  state_next<=S2;  end if;  when S3=> if load ='1' then  r7_next<=signed (r5_next)+2;  r8_next<=signed (r6_next)+2;  state_next<= S4;  else   state_next<=S3;  end if;  when S4=> if load ='1' then  r9_next<=signed (r7_next)+2;  r10_next<=signed (r8_next)+2;  state_next<=S5;  else   state_next<=S4;  end if;  when S5=> if load ='1' then  r11_next<=signed (r9_next)+2;  r12_next<=signed (r10_next)+2;  state_next<=S6;  else   state_next<=S5;  end if;      when S6=>   r13_next<=prod1;  r14_next<=prod2;  state_next<=S0;      end case;  end process p2;  CSA1: prod1 <= mult1*mult2;  CSA2: prod2<= mult3*mult4;      P3: process( state,r1,r2,r3,r4,r13,r14)  begin  case state is   when S6=>  mult1 <=signed (A); --R1,A1  mult2 <=signed (B); --R2,A2  when others =>  mult3<= r3; --R3  mult4 <=r4; -- R4  end case;  end process P3;    W<= std_logic_vector(prod1);     end Behavioral;   I want to multiply them together R1*R2. How do i do it? my testbench doesn't show any waveform

[Altera_Forum]

op <= (r3_next+2) * (r4_next+2);

[Altera_Forum]

--- Quote Start ---  op <= (r3_next+2) * (r4_next+2);  --- Quote End ---    I couldn't get any output after doing what you have said.   the following is my code   library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.All;  -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;  -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;  entity Project3M2A is  Port ( A : in STD_LOGIC_VECTOR (7 downto 0);  B : in STD_LOGIC_VECTOR (7 downto 0);  W : out STD_LOGIC_VECTOR (7 downto 0);  X : out STD_LOGIC_VECTOR (7 downto 0);  Y : out STD_LOGIC_VECTOR (7 downto 0);  Z : out STD_LOGIC_VECTOR (7 downto 0);  LOAD : in STD_LOGIC;  COMPLETE: out STD_LOGIC;  RST : in STD_LOGIC;  CLK : in STD_LOGIC); end Project3M2A;  architecture Behavioral of Project3M2A is   type state_type is (S0,S1,S2,S3,S4,S5,S6);--,S3,S4,S5,S6,S7,S8,S9,S10); signal state, state_next: state_type; signal add1_op0,add1_op1,add2_op0,add2_op1: signed ( 7 downto 0); signal mult1,mult2,mult3,mult4: signed (7 downto 0); signal R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12: signed (7 downto 0 );--R3,R4,R5,R6: std_logic_Vector (7 downto 0 ); signal R13,R14,R15,R16,R17,R18,R19,R20: signed (7 downto 0 ); -- Registers for doing X and + signal R1_next,R2_next,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next: signed( 7 downto 0);--,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next: std_logic Vector( 7 downto 0); signal R13_next,R14_next,R15_next: signed( 7 downto 0); signal prod1,prod2,prod3: signed (7 downto 0); begin   P1: process(clk,rst) is  begin  if rst='0' then  state<=S0;  r1 <= (others => '0');  r2 <= (others => '0');  r3 <= (others => '0');  r4 <= (others => '0');  r5 <= (others => '0');  r6 <= (others => '0');  r7 <= (others => '0');  r8 <= (others => '0');  r9 <= (others => '0');  r10 <= (others => '0');  r11 <= (others => '0');  r12 <= (others => '0');  r6 <= (others => '0');  r7 <= (others => '0');  elsif(clk'event and clk='1') then   state <=state_next; -- next state update  r1<=r1_next;-- update next state at rising edge of clk  r2<=r2_next;  r3<=r3_next;  r4<=r4_next;  r5<=r5_next;  r6<=r6_next;  r7<=r7_next;  r8<=r8_next;  r9<=r9_next;  r10<=r10_next;  r11<=r11_next;  r12<=r12_next;  r13<=r13_next;  r14<=r14_next;  end if; end process P1; P2: process (load, state,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14, A,B)  begin   r1_next<=r1;-- keep previous data if not updated  r2_next<=r2;  r3_next<=r3;  r4_next<=r4;  r5_next<=r5;  r6_next<=r6;  r7_next<=r7;  r8<=r8_next;  r9<=r9_next;  r10<=r10_next;  r11<=r11_next;  r12<=r12_next;  r13<=r13_next;  r14<=r14_next;  complete<='0';  case state is  when S0 => if load ='1' then  r1_next<= signed (A(7 downto 0));  r2_next<= signed (B(7 downto 0));  state_next<=S1;  complete<='1';  else  state_next<=S0;  end if;  when S1=> if load ='1' then  r3_next<=signed (A) +2;  r4_next<=signed (B) +2;  state_next<= S2;  --complete<='1';  else   state_next<=S1;  end if;  when S2=> if load ='1' then  r5_next<=signed (r3_next)+2;  r6_next<=signed (r4_next)+2;  state_next<=S3;  else  state_next<=S2;  end if;  when S3=> if load ='1' then  r7_next<=signed (r5_next)+2;  r8_next<=signed (r6_next)+2;  state_next<= S4;  else   state_next<=S3;  end if;  when S4=> if load ='1' then  r9_next<=signed (r7_next)+2;  r10_next<=signed (r8_next)+2;  state_next<=S5;  else   state_next<=S4;  end if;  when S5=> if load ='1' then  r11_next<=signed (r9_next)+2;  r12_next<=signed (r10_next)+2;  state_next<=S6;  else   state_next<=S5;  end if;      when S6=>   r13_next<=prod1;  r14_next<=prod2;  state_next<=S0;      end case;  end process p2;  CSA1: prod1 <= mult1*mult2;  CSA2: prod2<= mult3*mult4;      P3: process( state,r1,r2,r3,r4,r13,r14)  begin  case state is   when S6=>  mult1 <=signed (r1_next); --R1,A1  mult2 <=signed (r2_next); --R2,A2  when others =>  mult3<= r3_next; --R3  mult4 <=r4_next; -- R4  end case;  end process P3;    W<= std_logic_vector(prod1);    end Behavioral;

[Altera_Forum]

Output from what? 

Have you got a testbench?  Its not exactly clear what you're trying to do from the decription in the first post. It sounds like a simple adder to me - but you have some very complicated code..

[Altera_Forum]

I'm actually trying to do a matrix multiplication. But currently doing step by step and am stucked.  

 what if i want at S6 to have the multiplication of R1_NEXT AND R2_NEXT. This value is store in another register called R13_NEXT.  the value of R13_next does not show in my waveform. It is undefined.    when S6=> if load='1' then  r13_next<=(r1_next)*(r2_next);    state_next<=S0;  else  state_next<=S6;  END IF;        My test bench code:  LIBRARY ieee; USE ieee.std_logic_1164.ALL;  -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL;   ENTITY Project3M2A_TBW IS END Project3M2A_TBW;   ARCHITECTURE behavior OF Project3M2A_TBW IS     -- Component Declaration for the Unit Under Test (UUT)    COMPONENT Project3M2A  PORT(  A : IN std_logic_vector(7 downto 0);  B : IN std_logic_vector(7 downto 0);  W : OUT std_logic_vector(7 downto 0);  X : OUT std_logic_vector(7 downto 0);  Y : OUT std_logic_vector(7 downto 0);  Z : OUT std_logic_vector(7 downto 0);  LOAD : IN std_logic;  COMPLETE: OUT std_logic;  RST : IN std_logic;  CLK : IN std_logic  );  END COMPONENT;     --Inputs  signal A : std_logic_vector(7 downto 0) := (others => '0');  signal B : std_logic_vector(7 downto 0) := (others => '0');  signal LOAD : std_logic := '0';  signal RST : std_logic := '0';  signal CLK : std_logic := '0';     --Outputs  signal W : std_logic_vector(7 downto 0);  signal X : std_logic_vector(7 downto 0);  signal Y : std_logic_vector(7 downto 0);  signal Z : std_logic_vector(7 downto 0);  signal COMPLETE: std_logic :='0';  -- Clock period definitions  constant CLK_period : time := 40 ns;   BEGIN    -- Instantiate the Unit Under Test (UUT)  uut: Project3M2A PORT MAP (  A => A,  B => B,  W => W,  X => X,  Y => Y,  Z => Z,  LOAD => LOAD,  RST => RST,  CLK => CLK  );  A<="00000001";  B<="00000010";  load<=not load after 40ns;  -- Clock process definitions  CLK_process :process  begin  CLK <= '0';  wait for CLK_period/2;  CLK <= '1';  wait for CLK_period/2;  end process;      -- Stimulus process  stim_proc: process  begin  rst<='0';  wait for 60ns;   rst<='1';  wait for 100ns;  wait;  end process;  END;

[Altera_Forum]

This sounds like a good load of debugging is in order. 

 If r13_next is undefined, then the signals driving it are probably undefined. Trace them back to source.

[Altera_Forum]

Well, when i put this, R13_NEXT shows all zero 

when S6=> if load='1' then  r13_next<=signed ((r1_next)*(r2_next));  when i put this, r13_next shows undefined   when S6=> if load='1' then  r13_next<=((r1_next)*(r2_next));

[Altera_Forum]

I got the value when i put this code 

S6=> if load='1' then r13_next<=signed ((r1_next)*(r2_next));  since i put R1_next as "00000001" and R2_next as "00000010"; the multiplied value is " 00000000".. How do i do the multiplication in integer form?

[Altera_Forum]

Are you sure you're in the correct state to do that multiplication. 

 00000001 * 00000010 = 00000010  From your testebench LOAD toggles in line with the clock - I highly suggest making load synchronous to the clock.

[Altera_Forum]

--- Quote Start ---  Are you sure you're in the correct state to do that multiplication.  00000001 * 00000010 = 00000010  From your testebench LOAD toggles in line with the clock - I highly suggest making load synchronous to the clock.  --- Quote End ---     YES. After loading the values into the system. I want to use r1 which has value of 1 multiply with r2 which has value of 2. But since my r1&r2 is signed number. When doing R13= signed(r1*r2.) I get 00000000 instead of the value of the value 00000010 that i want. Because it did a binary multiplication. How do i make it into integer multiplication.  And how do i mske load synchronous to clock

[Altera_Forum]

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.All;  -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;  -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;  entity Project3M2A is  generic(lower: integer:=0; upper:integer:=127);   Port ( A : in STD_LOGIC_VECTOR (7 downto 0);  B : in STD_LOGIC_VECTOR (7 downto 0);  W : out STD_LOGIC_VECTOR (7 downto 0);  X : out STD_LOGIC_VECTOR (7 downto 0);  Y : out STD_LOGIC_VECTOR (7 downto 0);  Z : out STD_LOGIC_VECTOR (7 downto 0);  LOAD : in STD_LOGIC;  COMPLETE: out STD_LOGIC;  RST : in STD_LOGIC;  CLK : in STD_LOGIC); end Project3M2A;  architecture Behavioral of Project3M2A is   type state_type is (S0,S1,S2,S3,S4,S5);--,S3,S4,S5,S6,S7,S8,S9,S10); signal state, state_next: state_type; signal add1_op0,add1_op1,add2_op0,add2_op1: signed ( 7 downto 0); signal mult1,mult2,mult3,mult4,mult5, mult6: signed (7 downto 0); signal R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12: signed( 7 downto 0); signal R13,R14,R15: integer range lower to upper; --signal R13,R14,R15,R16,R17,R18,R19,R20: signed (7 downto 0 ); -- Registers for doing X and + signal R1_next,R2_next,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next: signed( 7 downto 0);--,R12_next,R13_next,R14_next,R15_next: signed( 7 downto 0);--,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next: std_logic Vector( 7 downto 0); signal R13_next,R14_next,R15_next: integer range lower to upper; signal prod1,prod2,prod3: signed (7 downto 0); signal sum1,sum2: signed (7 downto 0); begin   P1: process(clk,rst) is  begin  if rst='0' then  state<=S0;  r1 <= (others => '0');  r2 <= (others => '0');  r3 <= (others => '0');  r4 <= (others => '0');  r5 <= (others => '0');  r6 <= (others => '0');  r7 <= (others => '0');  r8 <= (others => '0');  r9 <= (others => '0');  r10 <= (others => '0');  r11 <= (others => '0');  r12 <= (others => '0');  --r13 <= (others => '0');  --r14 <= (others => '0');  --r15 <= (others => '0');    elsif(clk'event and clk='1' and load='1') then   state <= S1;  state <=state_next; -- next state update  r1<=r1_next;-- update next state at rising edge of clk  r2<=r2_next;  r3<=r3_next;  r4<=r4_next;  r5<=r5_next;  r6<=r6_next;  r7<=r7_next;  r8<=r8_next;  r9<=r9_next;  r10<=r10_next;  r11<=r11_next;  r12<=r12_next;  --r13<=r13_next;  --r14<=r14_next;  --r15<=r15_next;    end if; end process P1; P2: process (load,state,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,A,B)  begin   r1_next<=r1;-- keep previous data if not updated  r2_next<=r2;  r3_next<=r3;  r4_next<=r4;  r5_next<=r5;  r6_next<=r6;  r7_next<=r7;  r8<=r8_next;  r9<=r9_next;  r10<=r10_next;  r11<=r11_next;  r12<=r12_next;  r13<=r13_next;  r14<=r14_next;  r15<=r15_next;  complete<='0';  case state is  when S0 =>   r1_next<= signed (A(7 downto 0));  r2_next<= signed (B(7 downto 0));  state_next<=S1;    when S1=>   r3_next<=r1_next +2;  r4_next<=r2_next +2;  r13_next <= to_integer(r1_next);  r14_next <= to_integer(r2_next);  state_next<= S2;  complete<='1';    when S2=>   r15_next<= to_integer (r3_next);  r5_next<= r3_next+2;  r6_next<= r4_next+2;  state_next<=S3;   I tried to change signed value to integer but the value is wrong.. FOR R1_NEXT is declared as "00000001" and R2_NEXT declared as "00000010" But after i change it to integer it shows that R1_NEXT IS 1, R2_NEXT IS 10. HELP.... i want it to become decimal number. any clues on how i can do it?

[Altera_Forum]

right click on the signal in modelsim 

goto radix -> decimal.  If it's still 10 - there is a problem in your code - and YOU need to debug it.

[Altera_Forum]

--- Quote Start ---  right click on the signal in modelsim goto radix -> decimal.  If it's still 10 - there is a problem in your code - and YOU need to debug it.  --- Quote End ---     well, apparantly, i can use + but now * r13_next <= (unsigned(A) + unsigned(B)) --> gives me value of 3 r13_next <= (unsigned(A) *unsigned(B)) --> gives me value of undefine

[Altera_Forum]

Please post a copy of the waveform. 

 Also, why not try making a smaller file. r13_next <= (unsigned(A) *unsigned( B ) );  Will work just fine. There is clearly something wrong elsewhere in the code if you are getting a 'U' output. You need to debug the driving values.

[Altera_Forum]

this is my waveformhttp://www.alteraforum.com/forum/attachment.php?attachmentid=9698&stc=1  

  this is my test bench  ARCHITECTURE behavior OF Project3M2A_TBW IS     -- Component Declaration for the Unit Under Test (UUT)    COMPONENT Project3M2A  PORT(  A : IN std_logic_vector(7 downto 0);  B : IN std_logic_vector(7 downto 0);  W : OUT std_logic_vector(7 downto 0);  X : OUT std_logic_vector(7 downto 0);  Y : OUT std_logic_vector(7 downto 0);  Z : OUT std_logic_vector(7 downto 0);  -- P : INOUT std_logic_vector(7 downto 0);  LOAD : IN std_logic;  COMPLETE: OUT std_logic;  RST : IN std_logic;  CLK : IN std_logic  );  END COMPONENT;     --Inputs  signal A : std_logic_vector(7 downto 0) := (others => '0');  signal B : std_logic_vector(7 downto 0) := (others => '0');  signal LOAD : std_logic := '0';  signal RST : std_logic := '0';  signal CLK : std_logic := '0';     --Outputs  signal W : std_logic_vector(7 downto 0);  signal X : std_logic_vector(7 downto 0);  signal Y : std_logic_vector(7 downto 0);  signal Z : std_logic_vector(7 downto 0);  signal COMPLETE: std_logic :='0';  -- Clock period definitions  constant CLK_period : time := 40 ns;   BEGIN    -- Instantiate the Unit Under Test (UUT)  uut: Project3M2A PORT MAP (  A => A,  B => B,  W => W,  X => X,  Y => Y,  Z => Z,  LOAD => LOAD,  RST => RST,  CLK => CLK  );  A<="00000001";  B<="00000010";  load<=not load after 10ns;  -- Clock process definitions  CLK_process :process  begin  CLK <= '0';  wait for CLK_period/4;  CLK <= '1';  wait for CLK_period/4;  end process;      -- Stimulus process  stim_proc: process  begin  rst<='0';  wait for 5ns;   rst<='1';  wait for 10ns;  wait;  end process;   END;   Could it be the clock problem?    http://www.alteraforum.com/forum/attachment.php?attachmentid=9699&stc=1  This waveforms shows that after i did this ------ r13_next <=signed (signed(r1_next)* signed(r2_next)); it gave me output 0 is because it did binary AND operation? how do i make it to give me the ans 2. supposed to give me ans of (1*2) = 2.

[Altera_Forum]

Now try adding r1_next, r2_next and state to your waveform. how do you expect to debug without the whole picture? 

I dont even know what code you're using now.  If you post code, please use code tags.

[Altera_Forum]

This is my code....---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Project3M2A is --generic(lower: integer:=1; upper:integer:=127); Port ( A : in STD_LOGIC_VECTOR (7 downto 0); B : in STD_LOGIC_VECTOR (7 downto 0); W : out STD_LOGIC_VECTOR (7 downto 0); X : out STD_LOGIC_VECTOR (7 downto 0); Y : out STD_LOGIC_VECTOR (7 downto 0); Z : out STD_LOGIC_VECTOR (7 downto 0); LOAD : in STD_LOGIC; COMPLETE: out STD_LOGIC; RST : in STD_LOGIC; CLK : in STD_LOGIC); end Project3M2A; architecture Behavioral of Project3M2A is type state_type is (S0,S1,S2,S3,S4,S5,S6,S7);--,S3,S4,S5,S6,S7,S8,S9,S10); signal state, state_next: state_type; signal R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15: signed( 7 downto 0); signal R1_next,R2_next,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next,R13_next,R14_next,R15_next: signed( 7 downto 0);--,R12_next,R13_next,R14_next,R15_next: signed( 7 downto 0); begin P1: process(clk,rst) is begin if rst='0' then state<=S0; r1 <= (others => '0'); r2 <= (others => '0'); r3 <= (others => '0'); r4 <= (others => '0'); r5 <= (others => '0'); r6 <= (others => '0'); r7 <= (others => '0'); r8 <= (others => '0'); r9 <= (others => '0'); r10 <= (others => '0'); r11 <= (others => '0'); r12 <= (others => '0'); r13 <= (others => '0'); r14 <= (others => '0'); --r15 <= (others => '0'); elsif(clk'event and clk='1' and load='1') then state <= S1; state <=state_next; -- next state update r1<=r1_next;-- update next state at rising edge of clk r2<=r2_next; r3<=r3_next; r4<=r4_next; r5<=r5_next; r6<=r6_next; r7<=r7_next; r8<=r8_next; r9<=r9_next; r10<=r10_next; r11<=r11_next; r12<=r12_next; r13<=r13_next; r14<=r14_next; --r15<=r15_next; end if; end process P1; P2: PROCESS(load,state,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,A,B) begin case state is when S0 => r1_next<= SIGNED(A(7 downto 0)); r2_next<= SIGNED(B(7 downto 0)); state_next<=S1; when S1=> r3_next<=signed (A) +2; r4_next<=signed (B)+2; state_next<= S2; complete<='1'; when S2=> r5_next<= signed (r3_next)+2; r6_next<= signed (r4_next)+2; state_next<=S3; when S3=> r7_next<=signed (r5_next)+2; r8_next<=signed (r6_next)+2; state_next<= S4; when S4=> r9_next<=signed (r7_next)+2; r10_next<=signed (r8_next)+2; state_next<=S5; when S5=> r11_next<=signed (r9_next)+2; r12_next<=signed (r10_next)+2; state_next<=S6; when S6 => r13_next <=signed (signed(r1_next)* signed(r2_next)); --r14_next <= r3_next*r4_next; --r15_next <= r5_next*r6_next; state_next<=S7; when S7 => r14_next <=signed(signed(r3_next)* signed (r4_next)); state_next<=S0; end case; end process P2; W<= std_logic_vector(signed (r13_next)); end Behavioral;  

    this is my test bench code   -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; --use ieee.std_logic_arith.all; --USE ieee.std_logic_signed.ALL; --USE ieee.std_logic_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; ENTITY Project3M2A_TBW IS END Project3M2A_TBW; ARCHITECTURE behavior OF Project3M2A_TBW IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Project3M2A PORT( A : IN std_logic_vector(7 downto 0); B : IN std_logic_vector(7 downto 0); W : OUT std_logic_vector(7 downto 0); X : OUT std_logic_vector(7 downto 0); Y : OUT std_logic_vector(7 downto 0); Z : OUT std_logic_vector(7 downto 0); -- P : INOUT std_logic_vector(7 downto 0); LOAD : IN std_logic; COMPLETE: OUT std_logic; RST : IN std_logic; CLK : IN std_logic ); END COMPONENT; --Inputs signal A : std_logic_vector(7 downto 0) := (others => '0'); signal B : std_logic_vector(7 downto 0) := (others => '0'); signal LOAD : std_logic := '0'; signal RST : std_logic := '0'; signal CLK : std_logic := '0'; --Outputs signal W : std_logic_vector(7 downto 0); signal X : std_logic_vector(7 downto 0); signal Y : std_logic_vector(7 downto 0); signal Z : std_logic_vector(7 downto 0); signal COMPLETE: std_logic :='0'; -- Clock period definitions constant CLK_period : time := 50 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Project3M2A PORT MAP ( A => A, B => B, W => W, X => X, Y => Y, Z => Z, LOAD => LOAD, RST => RST, CLK => CLK ); A<="00000001"; B<="00000010"; load<=not load after 40ns; -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulus process stim_proc: process begin rst<='0'; wait for 5ns; rst<='1'; wait for 10ns; wait; end process; END;    This is my waveform http://www.alteraforum.com/forum/attachment.php?attachmentid=9701&stc=1    i need to have r13_next to be = 2.. but its showing zero in the waveform

[Altera_Forum]

Im not sure exactly what you're simulating, because your code has an error: 

r13_next <=signed (signed(r1_next)* signed(r2_next));  r13_next is only 8 bits. r1_next*r2_next gives a 16 bit result.  When modifed to  r13_next <=resize (r1_next* r2_next, 8);  It works just fine

[Altera_Forum]

OMG, THANKS TRICKY... 

You are my savior!!