Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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how to set the delay for an asynchronous input

lkg47
Начинающий
2 368Просмотр.
 

Hello, please help:

демодулятор_стробированием.png

async port --- "data"

pll clk --- clk_1

how to set constraints that define difference between delay lines "data ---> R3|clk" and "data --->R1|d"

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6 Ответы
KennyTan_Altera
Модератор
2 354Просмотр.

You may use set_data_delay, in the timing analyzer you type:


set_data_delay --help


You will see the description on it.


lkg47
Начинающий
2 351Просмотр.

invalid command name "set_data_delay"

quartus 15

ak6dn
Ценный участник III
2 346Просмотр.

Why would you use that circuit?

How are you going to use the output of R3? In what clock domain? Are you going to run it thru another dual rank synchronizer to access it in clock domain clk_1? Or what?

set_min_delay and set_max_delay are the sdc primitives you can use to constrain the net delays between the referenced ports.

Never heard of set_data_delay. Where is there a reference to that?

KennyTan_Altera
Модератор
2 338Просмотр.

set_data_delay was newly introduce. You may have to use the latest Quartus prime pro to check on it.


ak6dn
Ценный участник III
2 335Просмотр.

Hmmm. Only latest version of "Quartus Prime Pro" for set_data_delay.

Probably not useful then to 99.9% of people here.

KennyTan_Altera
Модератор
2 318Просмотр.

Sure.


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