illegal/unconstrained/constrained clocks

[Altera_Forum]

What does it mean when the clock I use everywhere in the design, which happens to be the output of a PLL, is shown as "illegal" in the timing analyser clock status summary? And the raw clock input that feeds only the PLL and nothing else, is shown as "unconstrained" ?

[Altera_Forum]

You need to constrain your input clock with a "create_clock command". 

Then you need to constrain the PLL output clocks, using the "derive_pll_clocks" command.