reg~feeder REMOVE?

[GOMEZ_IT]

Good morning.
I'm trying to make 2-register synchronizers for the metstability problem on asynchronous signals.
Quartus automatically inserts the LUT between one register and another which calls regx~feeder.
Is it possible through some attribute to eliminate this block and connect the 2 registers directly?
Regards, Luca

 

[sstrell]

It would be hard to figure this out without seeing the code you are using to create the synchronizer.

[ShengN_Intel]

Hi,

The branch line between the reg1 output and LOGIC_CELL_COMB where it connected to? May be can try to avoid that branch.

Thanks,

Best Regards,

Sheng

[FvM]

Hi,

it's just a misunderstanding respectively lack of knowledge about internal FPGA structure.

You are seeing "reg_feeders" in post mapping technology map. They are no separate FPGA hardware elements that can be intentionally used or omitted. They are integral part of FPGA logic element and simply belong to the DFF data path. Review device handbook LE chapter or  visualize implementation in resource property viewer (context menu "locate" in technology map).

The left block is combinational part of the locic cell (4-input LUT), just used as a buffer COMBOUT=DATAD in this case. 

[GOMEZ_IT]

Thanks everyone for the replies.
@FvM: between the output of the LUT (combout) and the input of the FLOP (datain) there is a switch.
Can this switch not be switched to exclude the LUT?
The photo I inserted in the first post is incorrect.
I attach the new one:

 

[GOMEZ_IT]

I also attach the VHDL code.
This is an edge detector on the falling edge with integrated flops for the CDC:

library ieee;
use ieee.std_logic_1164.all;
entity EdgeDetector is
port (
clk :in std_logic;
d :in std_logic;
edge :out std_logic
);
end EdgeDetector;
architecture EdgeDetector_rtl of EdgeDetector is

signal meta1 :std_logic:='0';
signal meta2 :std_logic:='0';
signal reg1 :std_logic:='0';
signal reg2 :std_logic:='0';

attribute altera_attribute : string;
attribute altera_attribute of meta1:signal is "-name PRESERVE_REGISTER ON; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS";
attribute altera_attribute of meta2:signal is "-name PRESERVE_REGISTER ON; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS";
attribute altera_attribute of reg1:signal is "-name PRESERVE_REGISTER ON; -name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS";
attribute altera_attribute of reg2:signal is "-name PRESERVE_REGISTER ON";

begin
reg: process(clk)
begin
if rising_edge(clk) then
meta1 <= d;
meta2 <= meta1;
reg1 <= meta2;
reg2 <= reg1;
edge <= (not reg1) and (reg2);
end if;
end process;
end EdgeDetector_rtl;

[FvM]

Hi,

between the output of the LUT (combout) and the input of the FLOP (datain) there is a switch.
Can this switch not be switched to exclude the LUT?

as far as I understand, the datapath you are referring to has a specific dedication for SLOAD function. There's an optional register chain datapath, but I don't know if it's available in the present situation.

Basically fitter is selecting the best available datapath automatically, particularly considering timing constraints. Why do you worry about fitter results? 

[GOMEZ_IT]

I don't need to achieve better results. 
I just wanted to understand if there are any constraints or attributes to pass to the 
synthesizer to connect the registers as desired.
Let's just say it's for educational purposes only

[FvM]

Hi,
Quartus provides quite limited features to manually control fitting and routing results. Review this recent thread discussing a similar problem https://community.intel.com/t5/Intel-Quartus-Prime-Software/Altera-Register-Chain/m-p/1497097

Consider that Quartus is designed to fit complex circuits in an optimal way. You probably should take it as granted that it has no features to command a specific implementation of trivial circuits.

Even if you use wysiwyg_lcell low primitives to describe your circuit, it won't be necessarily exactly implemented as coded. The register cascade data path isn't even present in the lcell primitive.

[FvM]

Hi,

I made an experiment with Cyclone 10 LP:

1. Implemented a register chain with cyclone10lp_ff wysiwyg primitives

2. Implemented a register chain with lpm_shiftreg
In both cases, datapath still goes through logic_cell_comb "reg feeder".

My guess, register chain path will be only used if logic_cell_comb is needed for other logic. Or it's not used by present Quartus versions at all.

[GOMEZ_IT]

HI,

I also experimented with the wysiwyg primitives for cycloneive and 
I confirm that the feeder is always inserted with quartus_std_22.1.
And trying to use certain pins of the flip-flop, 
like sdata/sload, to try to force not to use the feeder, 
quartus still ignores the mode in which I instantiated the primitive flipflop 
and connects it as he wants, without giving errors or warnings!!

[sstrell]

Have you tried removing the synchronizer identification attributes?  The Fitter may be adding the logic to preserve the synchronizer and maximize MTBF.  That might be what that logic is between the registers.

[GOMEZ_IT]

Yes, I tried, but to no avail.
Does anyone have experience with direct register chains on cycloneive?

[sstrell]

So even without any of the synthesis attributes, this is still happening?

[GOMEZ_IT]

YES