ARM A9 bare matal IRQ priority can't work

[TBaox]

I use cyclone V HPS, and there is a problem in configuring interrupt priority. I gave OSC1 TIMER a higher priority, and after the program was executed, I found that it could not preempt the low priority external interrupt from FPGA. Look at the priority configuration MASK and binary point are lower 3 bits. Excuse me, where is my configuration wrong.

The OSC1 timer runs normally as shown in figure 2. after the interrupt from FPGA is enabled, the timer interrupt cannot run normally, as shown in figure 1

[EBERLAZARE_I_Intel]

Hi,

Is the timer interrupt that you mentioned also could not run normal if if interrupt from other sources other than FPGA?

[TBaox]

I didn't try that.

But  IRQ from FPGA timer ip doesn't preempt the low priority external interrupt from FPGA pio,too.

So I think something wrong on my configation. 

[EBERLAZARE_I_Intel]

May I know which Quartus version you are using? Also how did you compile/setup your preloader files?

[TBaox]

Quartus Prime 17.1

and SOC EDS 17.1

[EBERLAZARE_I_Intel]

Hi,

Please check the ARM document on the Interrupt prioritization:

https://developer.arm.com/documentation/ddi0407/e/interrupt-controller/about-the-interrupt-controller/interrupt-types-and-sources

You  can also check out the example design below on GIC controller:

ftp://ftp.intel.com/pub/fpgaup/pub/Intel_Material/16.0/Tutorials/Using_GIC.pdf

[TBaox]

Sorry,I can't open the second link.

[EBERLAZARE_I_Intel]

Hi,

Unfortunately, the link is no longer available.

May I know, how did you setup/configure the prioritization? Did you have the H2f/f2h bridges enabled?

[TBaox]

I use this function and I have enabled H2f bridge and light H2F bridge, unuse f2H bridge. 

//set prioritization

alt_int_dist_priority_set(ALT_INT_INTERRUPT_F2S_FPGA_IRQ0,48);

[EBERLAZARE_I_Intel]

Hi,

The Priority interrupts, ID0-ID15, that can only be triggered by software called Software Generated Interrupts (SGI).

Unfortunately, we do not have any official document on how this can be done, thus please refer to below suggestion from other discussion on the SGI configuration:

https://stackoverflow.com/questions/20430733/inter-processor-interrrupts-in-arm-cortex-a9-how-to-write-an-handler-for-softw

https://stackoverflow.com/questions/41851975/enable-and-distribute-irqs-in-linux

[TBaox]

emmm，I think ID48 is not a SGI.

[EBERLAZARE_I_Intel]

Hi,

I found the documentation below on the Preemption on section 3.3, could you take a look:

https://developer.arm.com/documentation/ihi0048/bb

[TBaox]

OK，thanks