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ARM A9 bare matal IRQ priority can't work

TBaox
Beginner
1,094 Views

I use cyclone V HPS, and there is a problem in configuring interrupt priority. I gave OSC1 TIMER a higher priority, and after the program was executed, I found that it could not preempt the low priority external interrupt from FPGA. Look at the priority configuration MASK and binary point are lower 3 bits. Excuse me, where is my configuration wrong.

Inked微信图片_20210510110658_LI.jpg

微信图片_20210510111022.jpg

The OSC1 timer runs normally as shown in figure 2. after the interrupt from FPGA is enabled, the timer interrupt cannot run normally, as shown in figure 1

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EBERLAZARE_I_Intel
1,069 Views

Hi,

Is the timer interrupt that you mentioned also could not run normal if if interrupt from other sources other than FPGA?

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TBaox
Beginner
1,041 Views

I didn't try that.

But  IRQ from FPGA timer ip doesn't preempt the low priority external interrupt from FPGA pio,too.

So I think something wrong on my configation. 

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EBERLAZARE_I_Intel
1,025 Views

May I know which Quartus version you are using? Also how did you compile/setup your preloader files?

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TBaox
Beginner
1,012 Views
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EBERLAZARE_I_Intel
996 Views
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TBaox
Beginner
987 Views

Sorry,I can't open the second link.

 

 

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EBERLAZARE_I_Intel
971 Views

Hi,

 

Unfortunately, the link is no longer available.

 

May I know, how did you setup/configure the prioritization? Did you have the H2f/f2h bridges enabled?

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TBaox
Beginner
963 Views

I use this function and I have enabled H2f bridge and light H2F bridge, unuse f2H bridge. 

//set prioritization

alt_int_dist_priority_set(ALT_INT_INTERRUPT_F2S_FPGA_IRQ0,48);

 

 

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EBERLAZARE_I_Intel
944 Views

Hi,

 

The Priority interrupts, ID0-ID15, that can only be triggered by software called Software Generated Interrupts (SGI).

 

Unfortunately, we do not have any official document on how this can be done, thus please refer to below suggestion from other discussion on the SGI configuration:

https://stackoverflow.com/questions/20430733/inter-processor-interrrupts-in-arm-cortex-a9-how-to-write-an-handler-for-softw

https://stackoverflow.com/questions/41851975/enable-and-distribute-irqs-in-linux

 

 

 

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TBaox
Beginner
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EBERLAZARE_I_Intel
899 Views

Hi,

 

I found the documentation below on the Preemption on section 3.3, could you take a look:

https://developer.arm.com/documentation/ihi0048/bb

 

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TBaox
Beginner
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