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Hi sir
Intel Arria 10 GX (10AX115S2F45I1SG)
i am getting errors like
The source channel has 32 bits, while sink has 256 bits, for narrow to wide transfer, sink should have "empty" signal.
PFA screen shot.
here sink in ddr4 avalon- memory mapped interface
source is a pattern writer.
My question is how to add an optional empty signal in Avalon- Memory Mapped Interface (already mentioned in Interface Specification) in the sink side which I'm not able to add the Specific Signal in order to resolve the below error attached in the Screen Shot (in platform design).
Based on “An 812: Platform Designer System Design tutorial” calibration test done for Nios-2 processor and DDR4.
Now I'm Implementing the remaining modules which includes memory_tester_subsystem and Integrating with DDR 4 where I’m facing Data width mismatch between Pattern Writer which is (32 bits) and DDR4 memory Mapped interface which is (256 bits ) where we need to add the streaming Sink Signal mentioned in platform design.
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Hi Rakesh,
I cant see the error. Could you reattach the snapshot of the error?
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Hi SyafieqS_Intel
Thank you for your Response.
Please Find Attached Screen Shot.
reagrds
rakesh

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