MAX 10 ADC Sequencer Core Command Register Setting

[SJeon37]

Hi,​

I am testing the ADC in FPGA MAX 10 (10M50DAF484C6GES).

With reference to the example code below, it seems that the adc operation does not stop even if the RUN bit is set to 0.

I would like to know how to set the stop bit and how to set it in one cycle ADC mode.

Thank you for your help.

https://www.youtube.com/watch?v=u7y5ZR1E8SU

module sequencer ( Clock_qsys, Reset, AdcCsrAddress, //Address to CSR for ADC for setup AdcCsrReadEn, //Read enable for CSR for ADC for setup AdcCsrReadData, //Read data for CSR for ADC for setup AdcCsrWriteEn, //Write enable for CSR for ADC for setup AdcCsrWriteData, //Write data for CSR for ADC for setup reset_btn ); input Clock_qsys; input Reset; //Synchronous Reset output reg AdcCsrAddress; //Address to CSR for ADC for setup output reg AdcCsrReadEn; //Read enable for CSR for ADC for setup output reg [31: 0] AdcCsrReadData; //Read data for CSR for ADC for setup output reg AdcCsrWriteEn; //Write enable for CSR for ADC for setup output reg [31: 0] AdcCsrWriteData; //Write data for CSR for ADC for setup input reset_btn;   reg [2:0] CurrentState; reg [2:0] NextState;   initial begin CurrentState = 0; NextState = 0; end   always @(posedge Clock_qsys) begin // if(Reset) begin // CurrentState <= 0; // end else begin CurrentState <= NextState; // end end //Next state logic always @(CurrentState) begin //Default to not asserted AdcCsrAddress = 1'b0; AdcCsrReadEn = 1'b0; AdcCsrReadData = 32'b0; AdcCsrWriteEn = 1'b0; AdcCsrWriteData = 32'b0; case(CurrentState) 0, 1, 2, 3, 4, 5: //Go through delay chain to let ADC module finish reset NextState <= CurrentState + 1; 6 : //Write enable bit and finish begin AdcCsrWriteEn <= 1'b1; //Write data to CSR AdcCsrWriteData <= 32'h0000001; //Enable continuous run mode NextState <= CurrentState + 1; end 7 : //Write enable bit and finish begin AdcCsrAddress <= 1'b0; AdcCsrReadEn <= 1'b0; AdcCsrReadData <= 32'b0; AdcCsrWriteEn <= 1'b0; AdcCsrWriteData <= 32'b0; NextState <= 7; end endcase end   endmodule

[EngWei_O_Intel]

Hi SangCheol

Thanks for your inquiry. Allow me to take some time to go through your request and get back to you later.

Thanks.

Eng Wei

[EngWei_O_Intel]

Hi SangCheol

By looking at the sequencer design, seems not sufficient for me to articulate the issue. Do you mind to share with me the entire design? Are you testing it on a simulator or the actual hardware?

Thanks.

Eng Wei

[EngWei_O_Intel]

Hi SangCheol

We do not receive any response from you to the previous question that we need more details on the issue you are facing. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei