Component editor advice

[Altera_Forum]

I have an avalon memory slave with this simple interface (export side is not listed) 

              -- inputs from avalon:                 signal address : IN STD_LOGIC_VECTOR (18 DOWNTO 1);                 signal chipselect : IN STD_LOGIC;                 signal clk : IN STD_LOGIC;                 signal read : IN STD_LOGIC;                 signal write : IN STD_LOGIC;                 signal writedata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);                 signal byteenable : IN STD_LOGIC_VECTOR (3 DOWNTO 0);              -- outputs to avalon:                 signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);  In the component editor I can set separate read and write wait times however, I cant enter setup and hold timing parameters. These fields are grayed out. Why are they not enabled?   If I instantiate "Legacy component"-> "Interface to user logic" on the same hdl files I get the option of setting setup and hold and one wait time setting common for read and write.  Why are there this asymmetry in the tools? One tool can do one type which the other cant and vice versa. Both ought to have the "logic or" of these features.  Documentation is not clarifyng this neither component editor (http://www.altera.com/literature/hb/qts/qts_qii54005.pdf) nor developing components to sopc builder (http://www.altera.com/literature/hb/qts/qts_qii54007.pdf).

[Altera_Forum]

I would also like to set the setup and hold times for a custom component. Does anyone know how to do this? 

 Should I manually change the ptf file for the component?

[Altera_Forum]

Someone I work with found a solution. 

 The setup and hold times can be set, but only during the initial creation of the component. After it has been created the editor won't let you change the values.

[Altera_Forum]

Hello, 

 I’m not able to adjust setup and hold times during the initial creation or after that. Are there more tips and tricks for this topic?   System: Quartus II 5.0 (Web-Edition), Nios II 5.0 (Evaluation Version)   Regards, niosIIuser

[Altera_Forum]

Hi all, 

 I also have problems when designing user components. What I have figured out is: - if a waitrequest-signal is added, you cannot enter setup (and hold) times - there are some differences between 'Interface to User Logic' and 'Create New Component' - in 'Create New Component' setup times are not possible when units 'cycles' is selected (even if you add a clk signal as the dialog suggests) - in 'Interface to User Logic' you can enter setup and hold-times in 'cycles' but they are displayed in fractions of cycles This concerns Quartus / NIOS II Version 5.0. I also would like to have a hold time for read access to get a behaviour similar to Motorola Timing and other asynchronous MCUs. A problem is, that at the end of a read-cycle all signals leave their active state simultaneously and produce spikes in sub decoders (In my design NIOS replaces a 68k MCU). Are there any undocumented features?  Mike

[Altera_Forum]

Hello Mir 

 I also needed a read hold time to interface an isdn chip, the only solution was to add an extra delay by extra flipflops in the top bdf on the address lines. Also we had  an extra address bus for this chip. Altera should think about this.

[Altera_Forum]

There is a workaround: 

Generate your component as you would using the wizard "Create new component" in SOPC. Dont worry about your inabilty to control setup and hold times there. After finishing all your other SOPC details: Generated the system. Exit SOPC. Open the generated PTF file located in your root directory. The PFT file is a text file. Locate the section describing your component by searching for the name of your component: here usermod    MODULE usermod_0   {      class = "usermod";      class_version = "1.0"; .... removed stuff         }      }      SLAVE avalon_slave_0      {         SYSTEM_BUILDER_INFO         {            Bus_Type = "avalon";            Address_Width = "18";            Address_Alignment = "dynamic";            Data_Width = "32";            Has_Base_Address = "1";            Has_IRQ = "0";            Setup_Time = "1cycles";            Hold_Time = "2cycles";            Read_Wait_States = "3cycles";            Write_Wait_States = "4cycles";            Read_Latency = "0"; .... removed stuff Correct the setup/hold and read/write wait states to whatever value you require. The example has, 1,2, 3 and 4 cycles, respectively. Notice that the pulse width for the strobes (read or write) is one cycle longer as the corresponding value in the PTF file. The example has a write pulse of 4+1=5 cycles. This is reasonable, as wait_state means additional time to wait with respect to the minimum which is 1 cycle! Save the modified PTF file.  Start SOPC builder again. Dont modify anything with the system, but move to the last tab and generate the system. When done, exit SOPC. Your system is now ready for synthesis etc. Now, with the expected su/ho,wait values.  Important: Remember to correct the PTF file manually if for any reason you change anything in the SOPC builder. Any change in system configuration will create a new ptf file, and will thus overwrite your patch.  Warning: The "Create new component" wizard makes a directory in your root where it places you component, including its source files. Typically you would from "Create new component wizard" pick the source files from your root directory. Thats ok, but be warned that these files are no more the source for you user-logic. Your source is now in the component directory, so changing anything in the version in the root dir will have no effect. It will actually be overwritten when you generate your component. Why would you want to change your source code once the component has been generated? Because of another inconvenience in the "Create new component" wizard: You cant edit an already built component. Only start from scratch.... and redo the PTF etc... So for changes which does not break the interface of the component its ok to edit the source in the component directory. Remember though to generate in SOPC builder afterwards.  Background note: The PTF file is a textual description of the SOPC system. This file is built/created/edited by the SOPC builder during the first tab&#39;s. On the last tab, when you select GENERATE, this description, together with all the source files, is used to create all the verilog/vhdl descriptions of the system (CPU, RAMs, UARTS, USERLOGIC,,, and not least the AVALON INTERFACE)  MiR:<div class='quotetop'>QUOTE </div>  --- Quote Start ---  This concerns Quartus / NIOS II Version 5.0.[/b]  --- Quote End ---   Its unfortunate if this inconvenient implementation of the "Create new component" wizard present in quartus 4.2 has not been corrected in quartus 5.0. Hopefully it will come in the next release of SOPC builder.  Tip: To check these issues, make a minimalistic system consisting of a NIOS II/s, ram, rom and your user logic where the relevant avalon-pins are copied to user side (export type). Pilot it with just a couple of lines of C code to read/write from your user component. Simulate in quartus, and watch the avalon signals in the simulator. Notice that you should refrain from using an uart, as this may result in very long simulation time before the avalon-access takes place.  I hope these suggestions helps you get going until a more sound solution is provided.

[Altera_Forum]

I wrote: 

<div class='quotetop'>QUOTE </div>  --- Quote Start ---  Because of another inconvenience in the "Create new component" wizard: You cant edit an already built component. Only start from scratch.... and redo the PTF etc...[/b]  --- Quote End ---   this is wrong. You can edit a component, as clearly stated in the component editor manual (http://www.altera.com/literature/hb/qts/qts_qii54005.pdf) where its stated...  <div class='quotetop'>QUOTE </div>  --- Quote Start ---  To edit a component, right-click it in the list of available components, and choose Edit Component. You cannot edit components that were not created by the component editor, such as Altera®-provided components.[/b]  --- Quote End ---    I triede it but there seems to still be some problems with the setup and hold issue from the edited component. The edits seems not to be taken into acount in the ptf file for the system. So as far as I can see, you are still left with the manual-edit work-around suggested above.  All my tests are done with quartus 4.2 sp1 and sopc 4.2. I have no experience yet with latest release 5.0.