Error: Connected system ID hash not found on target at expected base address

[Altera_Forum]

Hello, 

 Usual sentence first: I'm fairly new to FPGA programming, so bear with me.  I tried to follow the Nios II Hardware Development Tutorial (version 3.0, Dec. 2009) using the latest (v 11.0) tools (Quartus II, Nios II Tools etc.) on Windows 7.  Everything works relatively smoothly (only problem is a timing issue with the JTAG, which I can't solve but can be ignored if I understand correctly). The .sof is written onto the FPGA. It consists of a cpu, onchip_mem, sysid, led_pio (it's a Cyclone III eval board), sys_clk_timer and a jtag uart.  The tutorial uses the count_binary sample and everything compiles without error. However, if I try to do Run As -> Nios II Hardware a windows pops open telling me "connected system id hash not found on target at expected base address."  If I click System ID Properties I get: Expected system ID base address: 0x11030 (which is the one in the SOPC builder) Expected system ID: 0x0 (which is the one in the SOPC builder) connected system id: not found Expected system timestamp: 1306314921 connected system timestamp: not found  I can see the connected USB-Blaster in the Processors and Byte Stream Devices panel.  Any suggestions would be much appreciated  U.

[Altera_Forum]

In the Target connection check the boxes ignore mismatch id and mismatch time stamp. 

Probably the sysid of ur sopc is not matching with the id in the nios2.It is a common issue.  Now I am working like that.It does not effect the design.

[Altera_Forum]

Hi, 

 If I tick the boxes in the Run As Configuration that makes Nios to ignore the ID and timestamp values from the sysid, I get an error saying "Downloading ELF process failed". I think there must be something wrong with the communication to the board, but can't figure out what it is.  Cheers, U.

[Altera_Forum]

Have you actually got the JTAG connection to the card working at all?

[Altera_Forum]

Sorry for being thick, but I don't know. I just follow the tutorial. I have no idea how to test if it's working or not. Unfortunately the tutorials don't tell you what you are actually doing, which I find very unsatisfactory. I just added the components and hoped it works to find out later what I actually did. 

 U.

[Altera_Forum]

Have you told the software what type of JTAG host interface you are using? 

(IIRC the options are USB, network etc)

[Altera_Forum]

Which software? SOPC Builder, Nios Tool, Quartus? All very confusing. How do I test the if the JTAG is working?

[Altera_Forum]

It s ok don't worry if you have followed any tutorial..the design are all correct. I have used them.. I know there is a problem of the error you are getting.I had the same problem but there is a work around to it. 

 First check  Do you have a jtag component in ur sopc..if not add it..did you donwload the hardware design in the fpga?? Donot terminate the programmer open sopc ,the time limited which is running.  Go to eclipse select perspective..goto debug configurations..check if u can see the cable which u are using to download..now debug it..donot run it..  I don't know the cause of the error but it woorks fine,there will be a warning of terminated but don't worry you can run it..use debug

[Altera_Forum]

OK, thanks for that. I get a new error message now, which says 

 "The system console model is invalid. Cannot launch."  But that could be because the programme count_binary seems to be written for different hardware test board. I have the Cyclone III starter kit and the programme addresses LCD etc, which don't exist on that one but the Cyclone III Development kit.  I'm still not sure if it's talking to the FPGA

[Altera_Forum]

Count_Binary connects to lcd and an led.If you have led it should work.Check the design for proper connections.

[Altera_Forum]

Yeah, it connects to 8 LEDs where I have only 4. I just want to run something simple to see if there is any connection between the Nios II Eclipse tool and the FPGA.  

 The error messages Altera provides are absolutely rubbish. They don't tell what is going wrong and they are nowhere referenced so that you look up where it comes from. I'm quite frustrated with this company already

[Altera_Forum]

I understand it I was in the same situation a month back. 

Are all the pin connections to the LEDs in the design correct.Verify from the board manual you would have got with the development kit.Because it is a sample design but may be not for your fpga chip pr board?Have you verified all the hardware connections are correct?Did you download the correct .sopc file with correct pin conigurations?Check in the pin planner.

[Altera_Forum]

Yeah, the pins are correct. I used this configuration for a simple verilog design and it worked. The sopc file is the one created during the tutorial. 

 Do you know where the "The system console model is invalid. Cannot launch." message comes from? The board or is it a communication error?   Do you have a simpler programme that I could test? Just one LED or so? Maybe I'll try to write that myself.

[Altera_Forum]

Try this 

 http://www.altera.com/literature/tt/tt_my_first_fpga.pdf  Check these threads:  http://www.alteraforum.com/forum/showthread.php?t=28791  http://www.alteraforum.com/forum/showthread.php?t=28971

[Altera_Forum]

The PDF is about a tutorial that doesn't involve the Nios II processor. I know that this would work as I had other verlilog designs running on the test board. 

 Having read the first thread I tried to download the .elf manually by typing:  nios2-download -g count_binary.elf  in the Nios II shell. Response: Pausig target processor: not responding. Resetting and trying again: FAILED Leaving target processor paused  The second thread contains an unanswered question of you.

[Altera_Forum]

Check the clocks and resets to your processor. That's normally what causes download failures. Less likely is that your memory system is broken.

[Altera_Forum]

There are some critical warnings about timings which didn't meet the specification. I read that I can ignore that as it has something to do with the JTAG. I was unable to solve these timing issues (again my lag of knowledge of FPGA programming etc).

[Altera_Forum]

Hi , 

 I am posting a design example which did run on my board.It is the complete design with an led but it is for cyclone 3.Modify it according to your fpga and its constraints.  Documentation:  http://www.altera.com/literature/tt/tt_nios2_hardware_tutorial.pdf

[Altera_Forum]

Found this one: 

 nios ii compact design (http://www.altera.com/support/examples/nios2/exm-nios-compact.html)  Works fine on the Cyclone III Starter Kit by just following the command line instruction in the tutorial section of the PDF.  Still don't know why the other one won't work.

[Altera_Forum]

--- Quote Start ---  There are some critical warnings about timings which didn't meet the specification. I read that I can ignore that as it has something to do with the JTAG. I was unable to solve these timing issues (again my lag of knowledge of FPGA programming etc).  --- Quote End ---  What are the failing paths? You can only ignore those messages if the failing paths are actually in the jtag components.

[Altera_Forum]

Since you failed to get the systemID and timestamp, a quite simple thing to complete, there is something wrong with the cpu and memory system. I just figure out the same problem as you have. Here is my experience for reference. 

 I checked my design carefully and found nothing doubtful, so I wondered why the cpu didn't respond to the PC. Oh, I forgot the reset signal and it was asserted forever by a switch. I flipped the switch and every thing worked.  So, figure out why your cpu doesn't respond the systemID inquiry, then you can advance to the next step.